Re: [PATCH 01/26] ppc: Add a POWER10 DD2 CPU

[Cédric Le Goater]

On 8/20/21 3:40 PM, Greg Kurz wrote:
> On Mon, 9 Aug 2021 15:45:22 +0200
> Cédric Le Goater <clg@kaod.org> wrote:
> 
>> The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit. DD1 doesn't have
>> HAIL but since it does not break the modeling and that we don't plan
>> to support DD1, modify the LPCR mask of all the POWER10 family.
>>
> 
> Maybe consider dropping DD1 at some point then ?

Sure. I will send a little series addressing all your comments since
the initial patches have been merged.

Thanks,

C. 


> 
> Anyway,
> 
> Reviewed-by: Greg Kurz <groug@kaod.org>
> 
>> Setting the HAIL bit is a requirement to support the scv instruction
>> on PowerNV POWER10 platforms since glibc-2.33.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>>  target/ppc/cpu-models.h | 1 +
>>  target/ppc/cpu-models.c | 4 +++-
>>  target/ppc/cpu_init.c   | 3 +++
>>  3 files changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
>> index fc5e21728d7e..095259275941 100644
>> --- a/target/ppc/cpu-models.h
>> +++ b/target/ppc/cpu-models.h
>> @@ -375,6 +375,7 @@ enum {
>>      CPU_POWERPC_POWER9_DD20        = 0x004E1200,
>>      CPU_POWERPC_POWER10_BASE       = 0x00800000,
>>      CPU_POWERPC_POWER10_DD1        = 0x00800100,
>> +    CPU_POWERPC_POWER10_DD20       = 0x00800200,
>>      CPU_POWERPC_970_v22            = 0x00390202,
>>      CPU_POWERPC_970FX_v10          = 0x00391100,
>>      CPU_POWERPC_970FX_v20          = 0x003C0200,
>> diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
>> index 87e4228614b0..4baa111713b0 100644
>> --- a/target/ppc/cpu-models.c
>> +++ b/target/ppc/cpu-models.c
>> @@ -776,6 +776,8 @@
>>                  "POWER9 v2.0")
>>      POWERPC_DEF("power10_v1.0",  CPU_POWERPC_POWER10_DD1,            
>> POWER10,
>>                  "POWER10 v1.0")
>> +    POWERPC_DEF("power10_v2.0",  CPU_POWERPC_POWER10_DD20,           
>> POWER10,
>> +                "POWER10 v2.0")
>>  #endif /* defined (TARGET_PPC64) */
>>  
>>  
>> /***************************************************************************/
>> @@ -952,7 +954,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
>>      { "power8", "power8_v2.0" },
>>      { "power8nvl", "power8nvl_v1.0" },
>>      { "power9", "power9_v2.0" },
>> -    { "power10", "power10_v1.0" },
>> +    { "power10", "power10_v2.0" },
>>  #endif
>>  
>>      /* Generic PowerPCs */
>> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
>> index 505a0ed6ac09..66deb18a6b65 100644
>> --- a/target/ppc/cpu_init.c
>> +++ b/target/ppc/cpu_init.c
>> @@ -8270,6 +8270,9 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
>>                               LPCR_DEE | LPCR_OEE))
>>          | LPCR_MER | LPCR_GTSE | LPCR_TC |
>>          LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
>> +    /* DD2 adds an extra HAIL bit */
>> +    pcc->lpcr_mask |= LPCR_HAIL;
>> +
>>      pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
>>      pcc->mmu_model = POWERPC_MMU_3_00;
>>  #if defined(CONFIG_SOFTMMU)
>