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Re: [PATCH 04/26] ppc/pnv: Use a simple incrementing index for the chip-
From: |
Cédric Le Goater |
Subject: |
Re: [PATCH 04/26] ppc/pnv: Use a simple incrementing index for the chip-id |
Date: |
Mon, 30 Aug 2021 09:11:47 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 |
On 8/20/21 3:51 PM, Greg Kurz wrote:
> On Mon, 9 Aug 2021 15:45:25 +0200
> Cédric Le Goater <clg@kaod.org> wrote:
>
>> When the QEMU PowerNV machine was introduced, multi chip support
>> modeled a two socket system with dual chip modules as found on some P8
>> Tuleta systems (8286-42A). But this is hardly used and not relevant
>> for QEMU. Use a simple index instead.
>>
>
> Makes sense.
>
>> With this change, we can now increase the max socket number to 16 as
>> found on high end systems.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> include/hw/ppc/pnv.h | 33 +++++++--------------------------
>> hw/ppc/pnv.c | 11 ++++++-----
>> 2 files changed, 13 insertions(+), 31 deletions(-)
>>
>> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
>> index 3fec7c87d82d..aa08d79d24de 100644
>> --- a/include/hw/ppc/pnv.h
>> +++ b/include/hw/ppc/pnv.h
>> @@ -174,25 +174,6 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
>> DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
>> TYPE_PNV_CHIP_POWER10)
>>
>> -/*
>> - * This generates a HW chip id depending on an index, as found on a
>> - * two socket system with dual chip modules :
>> - *
>> - * 0x0, 0x1, 0x10, 0x11
>> - *
>> - * 4 chips should be the maximum
>> - *
>> - * TODO: use a machine property to define the chip ids
>> - */
>> -#define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
>> -
>> -/*
>> - * Converts back a HW chip id to an index. This is useful to calculate
>> - * the MMIO addresses of some controllers which depend on the chip id.
>> - */
>> -#define PNV_CHIP_INDEX(chip) \
>> - (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
>> -
>> PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
>>
>> #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
>> @@ -256,11 +237,11 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
>> #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
>> #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull
>> #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \
>> - PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip)))
>> + PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
>>
>> #define PNV_HOMER_SIZE 0x0000000000400000ull
>> #define PNV_HOMER_BASE(chip) \
>> - (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE)
>> + (0x7ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE)
>>
>>
>> /*
>> @@ -279,16 +260,16 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
>> */
>> #define PNV_ICP_SIZE 0x0000000000100000ull
>> #define PNV_ICP_BASE(chip) \
>> - (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE)
>> + (0x0003ffff80000000ull + (uint64_t) (chip)->chip_id * PNV_ICP_SIZE)
>>
>>
>> #define PNV_PSIHB_SIZE 0x0000000000100000ull
>> #define PNV_PSIHB_BASE(chip) \
>> - (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) *
>> PNV_PSIHB_SIZE)
>> + (0x0003fffe80000000ull + (uint64_t)(chip)->chip_id * PNV_PSIHB_SIZE)
>>
>> #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull
>> #define PNV_PSIHB_FSP_BASE(chip) \
>> - (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \
>> + (0x0003ffe000000000ull + (uint64_t)(chip)->chip_id * \
>> PNV_PSIHB_FSP_SIZE)
>>
>> /*
>> @@ -324,11 +305,11 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
>> #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
>> #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull
>> #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \
>> - PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip)))
>> + PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
>>
>> #define PNV9_HOMER_SIZE 0x0000000000400000ull
>> #define PNV9_HOMER_BASE(chip) \
>> - (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE)
>> + (0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV9_HOMER_SIZE)
>>
>> /*
>> * POWER10 MMIO base addresses - 16TB stride per chip
>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>> index b122251d1a5d..025f01c55744 100644
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -809,9 +809,10 @@ static void pnv_init(MachineState *machine)
>> * TODO: should we decide on how many chips we can create based
>> * on #cores and Venice vs. Murano vs. Naples chip type etc...,
>> */
>> - if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) {
>> + if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) {
>> error_report("invalid number of chips: '%d'", pnv->num_chips);
>> - error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or
>> 4.\n");
>> + error_printf(
>> + "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and
>> 16.\n");
>> exit(1);
>> }
>>
>> @@ -819,6 +820,7 @@ static void pnv_init(MachineState *machine)
>> for (i = 0; i < pnv->num_chips; i++) {
>> char chip_name[32];
>> Object *chip = OBJECT(qdev_new(chip_typename));
>> + int chip_id = i;
>>
>> pnv->chips[i] = PNV_CHIP(chip);
>>
>> @@ -831,10 +833,9 @@ static void pnv_init(MachineState *machine)
>> &error_fatal);
>> }
>>
>> - snprintf(chip_name, sizeof(chip_name), "chip[%d]",
>> PNV_CHIP_HWID(i));
>> + snprintf(chip_name, sizeof(chip_name), "chip[%d]", chip_id);
>
> I'd rather pass directly the i variable. It is clear enough this is
> the index of the chip in pnv->chips[]. No need for an intermediate
> variable IMHO.
Yes. I will address that in a follow-up series.
Thanks,
C.
> Anyway,
>
> Reviewed-by: Greg Kurz <groug@kaod.org>
>
>> object_property_add_child(OBJECT(pnv), chip_name, chip);
>> - object_property_set_int(chip, "chip-id", PNV_CHIP_HWID(i),
>> - &error_fatal);
>> + object_property_set_int(chip, "chip-id", chip_id, &error_fatal);
>> object_property_set_int(chip, "nr-cores", machine->smp.cores,
>> &error_fatal);
>> object_property_set_int(chip, "nr-threads", machine->smp.threads,
>
- [PATCH 00/26] ppc/pnv: Extend the powernv10 machine, Cédric Le Goater, 2021/08/09
- [PATCH 04/26] ppc/pnv: Use a simple incrementing index for the chip-id, Cédric Le Goater, 2021/08/09
- [PATCH 03/26] ppc/pnv: powerpc_excp: Do not discard HDECR exception when entering power-saving mode, Cédric Le Goater, 2021/08/09
- [PATCH 07/26] ppc/xive: Export PQ get/set routines, Cédric Le Goater, 2021/08/09
- [PATCH 08/26] ppc/xive: Export xive_presenter_notify(), Cédric Le Goater, 2021/08/09
- [PATCH 02/26] ppc/pnv: Change the POWER10 machine to support DD2 only, Cédric Le Goater, 2021/08/09
- [PATCH 01/26] ppc: Add a POWER10 DD2 CPU, Cédric Le Goater, 2021/08/09
- [PATCH 13/26] ppc/pnv: Add POWER10 quads, Cédric Le Goater, 2021/08/09