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[PULL 18/54] target/ppc: Do not update nip on DFP instructions
From: |
David Gibson |
Subject: |
[PULL 18/54] target/ppc: Do not update nip on DFP instructions |
Date: |
Tue, 9 Nov 2021 16:51:28 +1100 |
From: Luis Pires <luis.pires@eldorado.org.br>
Before moving the existing DFP instructions to decodetree, drop the
nip update that shouldn't be done for these instructions.
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029192417.400707-9-luis.pires@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate/dfp-impl.c.inc | 8 --------
1 file changed, 8 deletions(-)
diff --git a/target/ppc/translate/dfp-impl.c.inc
b/target/ppc/translate/dfp-impl.c.inc
index e149777481..1431d955c6 100644
--- a/target/ppc/translate/dfp-impl.c.inc
+++ b/target/ppc/translate/dfp-impl.c.inc
@@ -15,7 +15,6 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
rd = gen_fprp_ptr(rD(ctx->opcode)); \
ra = gen_fprp_ptr(rA(ctx->opcode)); \
rb = gen_fprp_ptr(rB(ctx->opcode)); \
@@ -36,7 +35,6 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
ra = gen_fprp_ptr(rA(ctx->opcode)); \
rb = gen_fprp_ptr(rB(ctx->opcode)); \
gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
@@ -54,7 +52,6 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
uim = tcg_const_i32(UIMM5(ctx->opcode)); \
rb = gen_fprp_ptr(rB(ctx->opcode)); \
gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
@@ -72,7 +69,6 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
ra = gen_fprp_ptr(rA(ctx->opcode)); \
dcm = tcg_const_i32(DCM(ctx->opcode)); \
gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
@@ -90,7 +86,6 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
rt = gen_fprp_ptr(rD(ctx->opcode)); \
rb = gen_fprp_ptr(rB(ctx->opcode)); \
u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
@@ -114,7 +109,6 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
rt = gen_fprp_ptr(rD(ctx->opcode)); \
ra = gen_fprp_ptr(rA(ctx->opcode)); \
rb = gen_fprp_ptr(rB(ctx->opcode)); \
@@ -137,7 +131,6 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
rt = gen_fprp_ptr(rD(ctx->opcode)); \
rb = gen_fprp_ptr(rB(ctx->opcode)); \
gen_helper_##name(cpu_env, rt, rb); \
@@ -157,7 +150,6 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- gen_update_nip(ctx, ctx->base.pc_next - 4); \
rt = gen_fprp_ptr(rD(ctx->opcode)); \
rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
i32 = tcg_const_i32(i32fld(ctx->opcode)); \
--
2.33.1
- [PULL 12/54] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c, (continued)
- [PULL 12/54] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c, David Gibson, 2021/11/09
- [PULL 11/54] libdecnumber: introduce decNumberFrom[U]Int128, David Gibson, 2021/11/09
- [PULL 16/54] libdecnumber: Introduce decNumberIntegralToInt128, David Gibson, 2021/11/09
- [PULL 28/54] target/ppc: Move vcfuged to vmx-impl.c.inc, David Gibson, 2021/11/09
- [PULL 25/54] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] to decodetree, David Gibson, 2021/11/09
- [PULL 23/54] target/ppc: Move dqua[q], drrnd[q] to decodetree, David Gibson, 2021/11/09
- [PULL 26/54] ppc/pnv: Fix check on block device before updating drive contents, David Gibson, 2021/11/09
- [PULL 31/54] target/ppc: Implement vsldbi/vsrdbi instructions, David Gibson, 2021/11/09
- [PULL 06/54] target/ppc: Implement PLQ and PSTQ, David Gibson, 2021/11/09
- [PULL 17/54] target/ppc: Implement DCTFIXQQ, David Gibson, 2021/11/09
- [PULL 18/54] target/ppc: Do not update nip on DFP instructions,
David Gibson <=
- [PULL 38/54] target/ppc: receive high/low as argument in get/set_cpu_vsr, David Gibson, 2021/11/09
- [PULL 22/54] target/ppc: Move dquai[q], drint{x,n}[q] to decodetree, David Gibson, 2021/11/09
- [PULL 21/54] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] to decodetree, David Gibson, 2021/11/09
- [PULL 24/54] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] to decodetree, David Gibson, 2021/11/09
- [PULL 33/54] target/ppc: Implement Vector Insert Word from GPR using Immediate insns, David Gibson, 2021/11/09
- [PULL 34/54] target/ppc: Implement Vector Insert from VSR using GPR index insns, David Gibson, 2021/11/09
- [PULL 27/54] ppc/pegasos2: Suppress warning when qtest enabled, David Gibson, 2021/11/09
- [PULL 29/54] target/ppc: Implement vclzdm/vctzdm instructions, David Gibson, 2021/11/09
- [PULL 13/54] target/ppc: Introduce REQUIRE_FPU, David Gibson, 2021/11/09
- [PULL 19/54] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree, David Gibson, 2021/11/09