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[PATCH 03/35] softfloat: Add flag specific to Inf * 0
From: |
Richard Henderson |
Subject: |
[PATCH 03/35] softfloat: Add flag specific to Inf * 0 |
Date: |
Fri, 19 Nov 2021 17:04:30 +0100 |
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/fpu/softfloat-types.h | 1 +
fpu/softfloat-parts.c.inc | 4 ++--
fpu/softfloat-specialize.c.inc | 12 ++++++------
3 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index eaa12e1e00..56b4cf7835 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -153,6 +153,7 @@ enum {
float_flag_input_denormal = 0x0020,
float_flag_output_denormal = 0x0040,
float_flag_invalid_isi = 0x0080, /* inf - inf */
+ float_flag_invalid_imz = 0x0100, /* inf * 0 */
};
/*
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
index eb2b475ca4..3ed793347b 100644
--- a/fpu/softfloat-parts.c.inc
+++ b/fpu/softfloat-parts.c.inc
@@ -423,7 +423,7 @@ static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN
*b,
/* Inf * Zero == NaN */
if (unlikely(ab_mask == float_cmask_infzero)) {
- float_raise(float_flag_invalid, s);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
parts_default_nan(a, s);
return a;
}
@@ -489,6 +489,7 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a,
FloatPartsN *b,
if (unlikely(ab_mask != float_cmask_normal)) {
if (unlikely(ab_mask == float_cmask_infzero)) {
+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
goto d_nan;
}
@@ -567,7 +568,6 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a,
FloatPartsN *b,
goto finish_sign;
d_nan:
- float_raise(float_flag_invalid, s);
parts_default_nan(a, s);
return a;
}
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
index f2ad0f335e..943e3301d2 100644
--- a/fpu/softfloat-specialize.c.inc
+++ b/fpu/softfloat-specialize.c.inc
@@ -506,7 +506,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass
b_cls, FloatClass c_cls,
* the default NaN
*/
if (infzero && is_qnan(c_cls)) {
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
return 3;
}
@@ -533,7 +533,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass
b_cls, FloatClass c_cls,
* case sets InvalidOp and returns the default NaN
*/
if (infzero) {
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
return 3;
}
/* Prefer sNaN over qNaN, in the a, b, c order. */
@@ -556,7 +556,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass
b_cls, FloatClass c_cls,
* case sets InvalidOp and returns the input value 'c'
*/
if (infzero) {
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
return 2;
}
/* Prefer sNaN over qNaN, in the c, a, b order. */
@@ -580,7 +580,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass
b_cls, FloatClass c_cls,
* a default NaN
*/
if (infzero) {
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
return 2;
}
@@ -597,7 +597,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass
b_cls, FloatClass c_cls,
#elif defined(TARGET_RISCV)
/* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
if (infzero) {
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
}
return 3; /* default NaN */
#elif defined(TARGET_XTENSA)
@@ -606,7 +606,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass
b_cls, FloatClass c_cls,
* an input NaN if we have one (ie c).
*/
if (infzero) {
- float_raise(float_flag_invalid, status);
+ float_raise(float_flag_invalid | float_flag_invalid_imz, status);
return 2;
}
if (status->use_first_nan) {
--
2.25.1
- [RFC PATCH for-7.0 00/35] target/ppc fpu fixes and cleanups, Richard Henderson, 2021/11/19
- [PATCH 01/35] softfloat: Extend float_exception_flags to 16 bits, Richard Henderson, 2021/11/19
- [PATCH 04/35] softfloat: Add flags specific to Inf / Inf and 0 / 0, Richard Henderson, 2021/11/19
- [PATCH 02/35] softfloat: Add flag specific to Inf - Inf, Richard Henderson, 2021/11/19
- [PATCH 03/35] softfloat: Add flag specific to Inf * 0,
Richard Henderson <=
- [PATCH 07/35] softfloat: Add flag specific to signaling nans, Richard Henderson, 2021/11/19
- [PATCH 08/35] target/ppc: Update float_invalid_op_addsub for new flags, Richard Henderson, 2021/11/19
- [PATCH 05/35] softfloat: Add flag specific to sqrt(-x), Richard Henderson, 2021/11/19
- [PATCH 06/35] softfloat: Add flag specific to convert non-nan to int, Richard Henderson, 2021/11/19
- [PATCH 10/35] target/ppc: Update float_invalid_op_div for new flags, Richard Henderson, 2021/11/19
- [PATCH 11/35] target/ppc: Move float_check_status from FPU_FCTI to translate, Richard Henderson, 2021/11/19
- [PATCH 09/35] target/ppc: Update float_invalid_op_mul for new flags, Richard Henderson, 2021/11/19
- [PATCH 12/35] target/ppc: Update float_invalid_cvt for new flags, Richard Henderson, 2021/11/19
- [PATCH 15/35] target/ppc: Use FloatRoundMode in do_fri, Richard Henderson, 2021/11/19
- [PATCH 16/35] target/ppc: Tidy inexact handling in do_fri, Richard Henderson, 2021/11/19