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[PATCH 08/35] target/ppc: Update float_invalid_op_addsub for new flags
From: |
Richard Henderson |
Subject: |
[PATCH 08/35] target/ppc: Update float_invalid_op_addsub for new flags |
Date: |
Fri, 19 Nov 2021 17:04:35 +0100 |
Now that vxisi and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/fpu_helper.c | 38 ++++++++++++++------------------------
1 file changed, 14 insertions(+), 24 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index c4896cecc8..f0deada84b 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -450,13 +450,12 @@ void helper_reset_fpstatus(CPUPPCState *env)
set_float_exception_flags(0, &env->fp_status);
}
-static void float_invalid_op_addsub(CPUPPCState *env, bool set_fpcc,
- uintptr_t retaddr, int classes)
+static void float_invalid_op_addsub(CPUPPCState *env, int flags,
+ bool set_fpcc, uintptr_t retaddr)
{
- if ((classes & ~is_neg) == is_inf) {
- /* Magnitude subtraction of infinities */
+ if (flags & float_flag_invalid_isi) {
float_invalid_op_vxisi(env, set_fpcc, retaddr);
- } else if (classes & is_snan) {
+ } else if (flags & float_flag_invalid_snan) {
float_invalid_op_vxsnan(env, retaddr);
}
}
@@ -465,12 +464,10 @@ static void float_invalid_op_addsub(CPUPPCState *env,
bool set_fpcc,
float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2)
{
float64 ret = float64_add(arg1, arg2, &env->fp_status);
- int status = get_float_exception_flags(&env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
- if (unlikely(status & float_flag_invalid)) {
- float_invalid_op_addsub(env, 1, GETPC(),
- float64_classify(arg1) |
- float64_classify(arg2));
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_addsub(env, flags, 1, GETPC());
}
return ret;
@@ -480,12 +477,10 @@ float64 helper_fadd(CPUPPCState *env, float64 arg1,
float64 arg2)
float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2)
{
float64 ret = float64_sub(arg1, arg2, &env->fp_status);
- int status = get_float_exception_flags(&env->fp_status);
+ int flags = get_float_exception_flags(&env->fp_status);
- if (unlikely(status & float_flag_invalid)) {
- float_invalid_op_addsub(env, 1, GETPC(),
- float64_classify(arg1) |
- float64_classify(arg2));
+ if (unlikely(flags & float_flag_invalid)) {
+ float_invalid_op_addsub(env, flags, 1, GETPC());
}
return ret;
@@ -1616,9 +1611,8 @@ void helper_##name(CPUPPCState *env, ppc_vsr_t *xt,
\
env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
\
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
- float_invalid_op_addsub(env, sfprf, GETPC(), \
- tp##_classify(xa->fld) | \
- tp##_classify(xb->fld)); \
+ float_invalid_op_addsub(env, tstat.float_exception_flags, \
+ sfprf, GETPC()); \
} \
\
if (r2sp) { \
@@ -1660,9 +1654,7 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opcode,
env->fp_status.float_exception_flags |= tstat.float_exception_flags;
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
- float_invalid_op_addsub(env, 1, GETPC(),
- float128_classify(xa->f128) |
- float128_classify(xb->f128));
+ float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC());
}
helper_compute_fprf_float128(env, t.f128);
@@ -3278,9 +3270,7 @@ void helper_xssubqp(CPUPPCState *env, uint32_t opcode,
env->fp_status.float_exception_flags |= tstat.float_exception_flags;
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
- float_invalid_op_addsub(env, 1, GETPC(),
- float128_classify(xa->f128) |
- float128_classify(xb->f128));
+ float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC());
}
helper_compute_fprf_float128(env, t.f128);
--
2.25.1
- [RFC PATCH for-7.0 00/35] target/ppc fpu fixes and cleanups, Richard Henderson, 2021/11/19
- [PATCH 01/35] softfloat: Extend float_exception_flags to 16 bits, Richard Henderson, 2021/11/19
- [PATCH 04/35] softfloat: Add flags specific to Inf / Inf and 0 / 0, Richard Henderson, 2021/11/19
- [PATCH 02/35] softfloat: Add flag specific to Inf - Inf, Richard Henderson, 2021/11/19
- [PATCH 03/35] softfloat: Add flag specific to Inf * 0, Richard Henderson, 2021/11/19
- [PATCH 07/35] softfloat: Add flag specific to signaling nans, Richard Henderson, 2021/11/19
- [PATCH 08/35] target/ppc: Update float_invalid_op_addsub for new flags,
Richard Henderson <=
- [PATCH 05/35] softfloat: Add flag specific to sqrt(-x), Richard Henderson, 2021/11/19
- [PATCH 06/35] softfloat: Add flag specific to convert non-nan to int, Richard Henderson, 2021/11/19
- [PATCH 10/35] target/ppc: Update float_invalid_op_div for new flags, Richard Henderson, 2021/11/19
- [PATCH 11/35] target/ppc: Move float_check_status from FPU_FCTI to translate, Richard Henderson, 2021/11/19
- [PATCH 09/35] target/ppc: Update float_invalid_op_mul for new flags, Richard Henderson, 2021/11/19
- [PATCH 12/35] target/ppc: Update float_invalid_cvt for new flags, Richard Henderson, 2021/11/19
- [PATCH 15/35] target/ppc: Use FloatRoundMode in do_fri, Richard Henderson, 2021/11/19
- [PATCH 16/35] target/ppc: Tidy inexact handling in do_fri, Richard Henderson, 2021/11/19
- [PATCH 17/35] target/ppc: Clean up do_fri, Richard Henderson, 2021/11/19
- [PATCH 18/35] target/ppc: Update fmadd for new flags, Richard Henderson, 2021/11/19