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[PULL 005/101] target/ppc: ppc_store_fpscr doesn't update bits 0 to 28 a
From: |
Cédric Le Goater |
Subject: |
[PULL 005/101] target/ppc: ppc_store_fpscr doesn't update bits 0 to 28 and 52 |
Date: |
Thu, 16 Dec 2021 21:24:38 +0100 |
From: "Lucas Mateus Castro (alqotel)" <lucas.araujo@eldorado.org.br>
This commit fixes the difference reported in the bug in the reserved
bit 52, it does this by adding this bit to the mask of bits to not be
directly altered in the ppc_store_fpscr function (the hardware used to
compare to QEMU was a Power9).
The bits 0 to 27 were also added to the mask, as they are marked as
reserved in the PowerISA and bit 28 is a reserved extension of the DRN
field (bits 29:31) but can't be set using mtfsfi, while the other DRN
bits may be set using mtfsfi instruction, so bit 28 was also added to
the mask.
Although this is a difference reported in the bug, since it's a reserved
bit it may be a "don't care" case, as put in the bug report. Looking at
the ISA it doesn't explicitly mention this bit can't be set, like it
does for FEX and VX, so I'm unsure if this is necessary.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/266
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Message-Id: <20211201163808.440385-4-lucas.araujo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 4 ++++
target/ppc/cpu.c | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e946da5f3a8c..441d3dce194c 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -759,6 +759,10 @@ enum {
FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
FP_VXSQRT | FP_VXCVI)
+/* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */
+#define FPSCR_MTFS_MASK (~(MAKE_64BIT_MASK(36, 28) | PPC_BIT(28) | \
+ FP_FEX | FP_VX | PPC_BIT(52)))
+
/*****************************************************************************/
/* Vector status and control register */
#define VSCR_NJ 16 /* Vector non-java */
diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
index f933d9f2bd84..d7b42bae52d6 100644
--- a/target/ppc/cpu.c
+++ b/target/ppc/cpu.c
@@ -112,7 +112,7 @@ static inline void fpscr_set_rounding_mode(CPUPPCState *env)
void ppc_store_fpscr(CPUPPCState *env, target_ulong val)
{
- val &= ~(FP_VX | FP_FEX);
+ val &= FPSCR_MTFS_MASK;
if (val & FPSCR_IX) {
val |= FP_VX;
}
--
2.31.1
- [PULL v2 000/101] ppc queue, Cédric Le Goater, 2021/12/16
- [PULL 003/101] target/ppc: Fixed call to deferred exception, Cédric Le Goater, 2021/12/16
- [PULL 001/101] pseries: Update SLOF firmware image, Cédric Le Goater, 2021/12/16
- [PULL 010/101] ivshmem-test.c: enable test_ivshmem_server for ppc64 arch, Cédric Le Goater, 2021/12/16
- [PULL 002/101] hw/ppc/mac.h: Remove MAX_CPUS macro, Cédric Le Goater, 2021/12/16
- [PULL 004/101] test/tcg/ppc64le: test mtfsf, Cédric Le Goater, 2021/12/16
- [PULL 005/101] target/ppc: ppc_store_fpscr doesn't update bits 0 to 28 and 52,
Cédric Le Goater <=
- [PULL 009/101] ivshmem.c: change endianness to LITTLE_ENDIAN, Cédric Le Goater, 2021/12/16
- [PULL 027/101] target/ppc: Update float_invalid_op_addsub for new flags, Cédric Le Goater, 2021/12/16
- [PULL 026/101] softfloat: Add flag specific to signaling nans, Cédric Le Goater, 2021/12/16
- [PULL 012/101] docs: Minor updates on the powernv documentation., Cédric Le Goater, 2021/12/16
- [PULL 007/101] target/ppc: Implement Vector Extract Mask, Cédric Le Goater, 2021/12/16
- [PULL 011/101] pci-host: Allow extended config space access for PowerNV PHB4 model, Cédric Le Goater, 2021/12/16
- [PULL 006/101] target/ppc: Implement Vector Expand Mask, Cédric Le Goater, 2021/12/16
- [PULL 023/101] softfloat: Add flags specific to Inf / Inf and 0 / 0, Cédric Le Goater, 2021/12/16
- [PULL 025/101] softfloat: Add flag specific to convert non-nan to int, Cédric Le Goater, 2021/12/16
- [PULL 015/101] ppc/pnv.c: fix "system-id" FDT when -uuid is set, Cédric Le Goater, 2021/12/16