[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH] ppc/pnv: Fix number of registers in the PCIe controller on P

From: Cédric Le Goater
Subject: Re: [PATCH] ppc/pnv: Fix number of registers in the PCIe controller on POWER9
Date: Mon, 4 Apr 2022 08:53:45 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0

On 4/1/22 11:19, Frederic Barrat wrote:
The spec defines 3 registers, even though only index 0 and 2 are valid
on POWER9. The same model is used on POWER10. Register 1 is defined
there but we currently don't use it in skiboot. So we can keep
reporting an error on write.

Reported by Coverity (CID 1487176).

Fixes: 4f9924c4d4cf ("ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge")
Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
  include/hw/pci-host/pnv_phb4.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

Queued for ppc-7.0



diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index b02ecdceaa..19dcbd6f87 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -180,7 +180,7 @@ struct PnvPhb4PecState {
      MemoryRegion nest_regs_mr;
/* PCI registers, excluding per-stack */
-#define PHB4_PEC_PCI_REGS_COUNT     0x2
+#define PHB4_PEC_PCI_REGS_COUNT     0x3
      uint64_t pci_regs[PHB4_PEC_PCI_REGS_COUNT];
      MemoryRegion pci_regs_mr;

reply via email to

[Prev in Thread] Current Thread [Next in Thread]