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Re: [RFC PATCH v2 4/7] target/ppc: Implemented xvf*ger*


From: Lucas Mateus Martins Araujo e Castro
Subject: Re: [RFC PATCH v2 4/7] target/ppc: Implemented xvf*ger*
Date: Mon, 9 May 2022 08:33:38 -0300
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.1


On 08/05/2022 01:03, Richard Henderson wrote:


On 5/6/22 07:18, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)" <lucas.araujo@eldorado.org.br>

Implement the following PowerISA v3.1 instructions:
xvf32ger:   VSX Vector 32-bit Floating-Point GER (rank-1 update)
xvf32gernn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative
multiply, Negative accumulate
xvf32gernp: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative
multiply, Positive accumulate
xvf32gerpn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive
multiply, Negative accumulate
xvf32gerpp: VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive
multiply, Positive accumulate
xvf64ger:   VSX Vector 64-bit Floating-Point GER (rank-1 update)
xvf64gernn: VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative
multiply, Negative accumulate
xvf64gernp: VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative
multiply, Positive accumulate
xvf64gerpn: VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive
multiply, Negative accumulate
xvf64gerpp: VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive
multiply, Positive accumulate

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
---
  target/ppc/cpu.h                    |   4 +
  target/ppc/fpu_helper.c             | 178 ++++++++++++++++++++++++++++
  target/ppc/helper.h                 |  10 ++
  target/ppc/insn32.decode            |  13 ++
  target/ppc/translate/vsx-impl.c.inc |  12 ++
  5 files changed, 217 insertions(+)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 348a898950..eb50ad699e 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2639,6 +2639,8 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx)
  #define VsrSW(i) s32[i]
  #define VsrD(i) u64[i]
  #define VsrSD(i) s64[i]
+#define VsrSF(i) f32[i]
+#define VsrDF(i) f64[i]
  #else
  #define VsrB(i) u8[15 - (i)]
  #define VsrSB(i) s8[15 - (i)]
@@ -2648,6 +2650,8 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx)
  #define VsrSW(i) s32[3 - (i)]
  #define VsrD(i) u64[1 - (i)]
  #define VsrSD(i) s64[1 - (i)]
+#define VsrSF(i) f32[3 - (i)]
+#define VsrDF(i) f64[1 - (i)]
  #endif

  static inline int vsr64_offset(int i, bool high)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index f6c8318a71..138b30d08f 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -3462,3 +3462,181 @@ void helper_xssubqp(CPUPPCState *env, uint32_t opcode,
      *xt = t;
      do_float_check_status(env, GETPC());
  }
+
+static void set_rounding_mode_rn(CPUPPCState *env)
+{
+    uint8_t rmode = (env->fpscr & FP_RN) >> FPSCR_RN0;
+    switch (rmode) {
+    case 0:
+        set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
+        break;
+    case 1:
+        set_float_rounding_mode(float_round_to_zero, &env->fp_status);
+        break;
+    case 2:
+        set_float_rounding_mode(float_round_up, &env->fp_status);
+        break;
+    case 3:
+        set_float_rounding_mode(float_round_down, &env->fp_status);
+        break;
+    default:
+        abort();
+    }
+}

How is this different from fpscr_set_rounding_mode and why do you need to call it at all?
It's not, I was worried that my tests weren't getting some edge case and searching in target/ppc/fpu_helper.c I couldn't find a function to set the rounding mode so I decided to create this one, but looking back now it's completely unnecessary so I'll remove it in v3.


r~
--
Lucas Mateus M. Araujo e Castro
Instituto de Pesquisas ELDORADO
Departamento Computação Embarcada
Analista de Software Trainee
Aviso Legal - Disclaimer

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