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Re: [PATCH] pnv/xive2: Access direct mapped thread contexts from all chi

From: Frederic Barrat
Subject: Re: [PATCH] pnv/xive2: Access direct mapped thread contexts from all chips
Date: Thu, 2 Jun 2022 19:06:23 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.0

On 02/06/2022 19:00, Cédric Le Goater wrote:
On 6/2/22 18:53, Frederic Barrat wrote:
When accessing a thread context through the IC BAR, the offset of the
page in the BAR identifies the CPU. From that offset, we can compute
the PIR (processor ID register) of the CPU to do the data structure
lookup. On P10, the current code assumes an access for node 0 when
computing the PIR. Everything is almost in place to allow access for
other nodes though. So this patch reworks how the PIR value is
computed so that we can access all thread contexts through the IC BAR.

The PIR is already correct on P9, so no need to modify anything there.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Is that a P10 bug ? If so, a fixes tag is needed.

Fixes: da71b7e3ed45 ("ppc/pnv: Add a XIVE2 controller to the POWER10 chip")

Daniel, good enough or you prefer a resend?


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