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Re: [PATCH 2/3] target/ppc: Improve Radix xlate level validation

From: Leandro Lupori
Subject: Re: [PATCH 2/3] target/ppc: Improve Radix xlate level validation
Date: Fri, 24 Jun 2022 10:22:10 -0300
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On 6/21/22 18:21, Fabiano Rosas wrote:
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Leandro Lupori <leandro.lupori@eldorado.org.br> writes:

Check if the number and size of Radix levels are valid on
POWER9/POWER10 CPUs, according to the supported Radix Tree
Configurations described in their User Manuals.

Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
  target/ppc/mmu-radix64.c | 36 +++++++++++++++++++++++++++++-------
  1 file changed, 29 insertions(+), 7 deletions(-)

diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index 9a8a2e2875..2f0bcbfe2e 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -236,13 +236,31 @@ static void ppc_radix64_set_rc(PowerPCCPU *cpu, 
MMUAccessType access_type,

+static bool ppc_radix64_is_valid_level(int level, int psize, uint64_t nls)

I wonder if we should take the time to make this per-CPU now to prepare
for any future CPU that supports a different layout.

The downside would be that we would already take a performance hit by calling this function through a CPU class pointer. It would also prevent compiler optimizations that are possible with local static functions.

I can leave a comment in ppc_radix64_is_valid_level, suggesting the addition of a new CPU class method, if a new CPU that supports other Radix configurations is added (e.g., Microwatt).


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