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Re: [PULL 14/20] hw/ppc/pegasos2: Fix PCI interrupt routing

From: BALATON Zoltan
Subject: Re: [PULL 14/20] hw/ppc/pegasos2: Fix PCI interrupt routing
Date: Wed, 8 Mar 2023 15:46:47 +0100 (CET)

On Wed, 8 Mar 2023, Philippe Mathieu-Daudé wrote:
Hi Zoltan,

On 8/3/23 00:47, Philippe Mathieu-Daudé wrote:
From: BALATON Zoltan <balaton@eik.bme.hu>

According to the PegasosII schematics the PCI interrupt lines are
connected to both the gpp pins of the Mv64361 north bridge and the
PINT pins of the VT8231 south bridge so guests can get interrupts from
either of these. So far we only had the MV64361 connections which
worked for on board devices but for additional PCI devices (such as
network or sound card added with -device) guest OSes expect interrupt
from the ISA IRQ 9 where the firmware routes these PCI interrupts in
VT8231 ISA bridge. After the previous patches we can now model this
and also remove the board specific connection from mv64361. Also
configure routing of these lines when using Virtual Open Firmware to
match board firmware for guests that expect this.

IIUC the schematic, only tje INTA and INTB lines (AGP IRQs) are
bidirectional and shared between NB/SB.

INTC and INTC are SB output to NB input.

I'll check the schematics again when I have time later but what we know for sure is that guests expect PCI interrupts to raise ISA IRQ9 which is mapped by the VT8231 ISA function 0c55-0x57 registers. The PCI buses are otherwise handled by the north bridge. So how can the VIA PINT pins be outputs? Where do the signals from the PCI cards go into VT8231 otherwise? Also the VT8231 datasheet on page 10 says PINTA-D pins are inputs so I can't understand your reasoning above.


This fixes PCI interrupts on pegasos2 under Linux, MorphOS and AmigaOS.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Tested-by: Rene Engel <ReneEngel80@emailn.de>
Message-Id: <520ff9e6eeef600ee14a4116c0c7b11940cc499c.1678188711.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
  hw/pci-host/mv64361.c |  4 ----
  hw/ppc/pegasos2.c     | 26 +++++++++++++++++++++++++-
  2 files changed, 25 insertions(+), 5 deletions(-)

diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c
index 298564f1f5..19e8031a3f 100644
--- a/hw/pci-host/mv64361.c
+++ b/hw/pci-host/mv64361.c
@@ -873,10 +873,6 @@ static void mv64361_realize(DeviceState *dev, Error **errp)
      sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cpu_irq);
      qdev_init_gpio_in_named(dev, mv64361_gpp_irq, "gpp", 32);
-    /* FIXME: PCI IRQ connections may be board specific */
-    for (i = 0; i < PCI_NUM_PINS; i++) {
-        s->pci[1].irq[i] = qdev_get_gpio_in_named(dev, "gpp", 12 + i);
-    }
    static void mv64361_reset(DeviceState *dev)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index 7cc375df05..f1650be5ee 100644
--- a/hw/ppc/pegasos2.c
+++ b/hw/ppc/pegasos2.c
@@ -73,6 +73,8 @@ struct Pegasos2MachineState {
      MachineState parent_obj;
      PowerPCCPU *cpu;
      DeviceState *mv;
+    qemu_irq mv_pirq[PCI_NUM_PINS];
+    qemu_irq via_pirq[PCI_NUM_PINS];
      Vof *vof;
      void *fdt_blob;
      uint64_t kernel_addr;
@@ -95,6 +97,15 @@ static void pegasos2_cpu_reset(void *opaque)
  +static void pegasos2_pci_irq(void *opaque, int n, int level)

So this handler is only for A/B. We could rename it pegasos2_agp_irq()
and only wire it to the first 2 pins, but I since we can only register
one handler per bus, simpler to ...

+    Pegasos2MachineState *pm = opaque;
+    /* PCI interrupt lines are connected to both MV64361 and VT8231 */
+    qemu_set_irq(pm->mv_pirq[n], level);

... add a 'if (n < 2)' check here.

+    qemu_set_irq(pm->via_pirq[n], level);

@@ -156,11 +167,18 @@ static void pegasos2_init(MachineState *machine)
      /* Marvell Discovery II system controller */
      pm->mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1,
qdev_get_gpio_in(DEVICE(pm->cpu), PPC6xx_INPUT_INT)));
+    for (i = 0; i < PCI_NUM_PINS; i++) {
+        pm->mv_pirq[i] = qdev_get_gpio_in_named(pm->mv, "gpp", 12 + i);
+    }
      pci_bus = mv64361_get_pci_bus(pm->mv, 1);
+    pci_bus_irqs(pci_bus, pegasos2_pci_irq, pm, PCI_NUM_PINS);
        /* VIA VT8231 South Bridge (multifunction PCI device) */
via = OBJECT(pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0),
                                                   true, TYPE_VT8231_ISA));
+    for (i = 0; i < PCI_NUM_PINS; i++) {

I'd rather declare as via_pirq[2] and iterate over ARRAY_SIZE() here
(and also use ARRAY_SIZE() in the new check in pegasos2_pci_irq).

+        pm->via_pirq[i] = qdev_get_gpio_in_named(DEVICE(via), "pirq", i);
+    }

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