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From: | Fabiano Rosas |
Subject: | Re: [PATCH v2 3/6] target/ppc: Fix instruction loading endianness in alignment interrupt |
Date: | Fri, 31 Mar 2023 18:27:56 -0300 |
Nicholas Piggin <npiggin@gmail.com> writes: > powerpc ifetch endianness depends on MSR[LE] so it has to byteswap > after cpu_ldl_code(). This corrects DSISR bits in alignment > interrupts when running in little endian mode. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Fabiano Rosas <farosas@suse.de>
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