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Re: [PATCH v8 2/3] hw/ppc: Add N1 chiplet model

From: Cédric Le Goater
Subject: Re: [PATCH v8 2/3] hw/ppc: Add N1 chiplet model
Date: Tue, 12 Dec 2023 10:41:09 +0100
User-agent: Mozilla Thunderbird

On 12/8/23 16:19, Chalapathi V wrote:
The N1 chiplet handle the high speed i/o traffic over PCIe and others.
The N1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.

This commit creates a N1 chiplet model and initialize and realize the
pervasive chiplet model where chiplet control registers are implemented.

This commit also implement the read/write method for the powerbus scom

Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>



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