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[PULL 02/72] ppc/spapr: Add ibm,pi-features
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From: |
Nicholas Piggin |
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Subject: |
[PULL 02/72] ppc/spapr: Add ibm,pi-features |
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Date: |
Fri, 24 May 2024 09:06:35 +1000 |
The ibm,pi-features property has a bit to say whether or not
msgsndp should be used. Linux checks if it is being run under
KVM and avoids msgsndp anyway, but it would be preferable to
rely on this bit.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index d2d1e310a3..4345764bce 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -353,6 +353,32 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
_FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
}
+static void spapr_dt_pi_features(SpaprMachineState *spapr,
+ PowerPCCPU *cpu,
+ void *fdt, int offset)
+{
+ uint8_t pi_features[] = { 1, 0,
+ 0x00 };
+
+ if (kvm_enabled() && ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00,
+ 0, cpu->compat_pvr)) {
+ /*
+ * POWER9 and later CPUs with KVM run in LPAR-per-thread mode where
+ * all threads are essentially independent CPUs, and msgsndp does not
+ * work (because it is physically-addressed) and therefore is
+ * emulated by KVM, so disable it here to ensure XIVE will be used.
+ * This is both KVM and CPU implementation-specific behaviour so a KVM
+ * cap would be cleanest, but for now this works. If KVM ever permits
+ * native msgsndp execution by guests, a cap could be added at that
+ * time.
+ */
+ pi_features[2] |= 0x08; /* 4: No msgsndp */
+ }
+
+ _FDT((fdt_setprop(fdt, offset, "ibm,pi-features", pi_features,
+ sizeof(pi_features))));
+}
+
static hwaddr spapr_node0_size(MachineState *machine)
{
if (machine->numa_state->num_nodes) {
@@ -815,6 +841,8 @@ static void spapr_dt_cpu(CPUState *cs, void *fdt, int
offset,
spapr_dt_pa_features(spapr, cpu, fdt, offset);
+ spapr_dt_pi_features(spapr, cpu, fdt, offset);
+
_FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
cs->cpu_index / vcpus_per_socket)));
--
2.43.0
- [PULL 00/72] ppc-for-9.1-1 queue, Nicholas Piggin, 2024/05/23
- [PULL 01/72] spapr: avoid overhead of finding vhyp class in critical operations, Nicholas Piggin, 2024/05/23
- [PULL 02/72] ppc/spapr: Add ibm,pi-features,
Nicholas Piggin <=
- [PULL 03/72] target/ppc: Fix broadcast tlbie synchronisation, Nicholas Piggin, 2024/05/23
- [PULL 04/72] tcg/cputlb: Remove non-synced variants of global TLB flushes, Nicholas Piggin, 2024/05/23
- [PULL 05/72] tcg/cputlb: remove other-cpu capability from TLB flushing, Nicholas Piggin, 2024/05/23
- [PULL 06/72] target/ppc: Move sync instructions to decodetree, Nicholas Piggin, 2024/05/23
- [PULL 07/72] target/ppc: Fix embedded memory barriers, Nicholas Piggin, 2024/05/23
- [PULL 08/72] target/ppc: Add ISA v3.1 variants of sync instruction, Nicholas Piggin, 2024/05/23
- [PULL 11/72] target/ppc: Move mul{li, lw, lwo, hw, hwu} instructions to decodetree., Nicholas Piggin, 2024/05/23
- [PULL 12/72] target/ppc: Make divw[u] handler method decodetree compatible., Nicholas Piggin, 2024/05/23
- [PULL 09/72] target/ppc: Merge various fpu helpers, Nicholas Piggin, 2024/05/23
- [PULL 10/72] target/ppc: Move floating-point arithmetic instructions to decodetree., Nicholas Piggin, 2024/05/23