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[PULL 03/72] target/ppc: Fix broadcast tlbie synchronisation
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From: |
Nicholas Piggin |
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Subject: |
[PULL 03/72] target/ppc: Fix broadcast tlbie synchronisation |
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Date: |
Fri, 24 May 2024 09:06:36 +1000 |
With mttcg, broadcast tlbie instructions do not wait until other vCPUs
have been kicked out of TCG execution before they complete (including
necessary subsequent tlbsync, etc., instructions). This is contrary to
the ISA, and it permits other vCPUs to use translations after the TLB
flush. For example:
CPU0
// *memP is initially 0, memV maps to memP with *pte
*pte = 0;
ptesync ; tlbie ; eieio ; tlbsync ; ptesync
*memP = 1;
CPU1
assert(*memV == 0);
It is possible for the assertion to fail because CPU1 translates memV
using the TLB after CPU0 has stored 1 to the underlying memory. This
race was observed with a careful test case where CPU1 checks run in a
very large expensive TB so it can run for the entire CPU0 period between
clearing the pte and storing the memory, but host vCPU thread preemption
could cause the race to hit anywhere.
As explained in commit 4ddc104689b ("target/ppc: Fix tlbie"), it is not
enough to just use tlb_flush_all_cpus_synced(), because that does not
execute until the calling CPU has finished its TB. It is also required
that the TB is ended at the point where the TLB flush must subsequently
take effect.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/helper_regs.c | 2 +-
target/ppc/mmu_helper.c | 2 +-
target/ppc/translate.c | 7 +++++++
target/ppc/translate/storage-ctrl-impl.c.inc | 7 +++++++
4 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 25258986e3..9094ae5004 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -334,7 +334,7 @@ void check_tlb_flush(CPUPPCState *env, bool global)
if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) {
env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH;
env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
- tlb_flush_all_cpus(cs);
+ tlb_flush_all_cpus_synced(cs);
return;
}
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index b35a93c198..d9d950e220 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -534,7 +534,7 @@ void helper_tlbie_isa300(CPUPPCState *env, target_ulong rb,
target_ulong rs,
if (local) {
tlb_flush_page(env_cpu(env), addr);
} else {
- tlb_flush_page_all_cpus(env_cpu(env), addr);
+ tlb_flush_page_all_cpus_synced(env_cpu(env), addr);
}
return;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 49dee6cab0..24461c2d1b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3494,6 +3494,13 @@ static inline void gen_check_tlb_flush(DisasContext
*ctx, bool global)
gen_helper_check_tlb_flush_local(tcg_env);
}
gen_set_label(l);
+ if (global) {
+ /*
+ * Global TLB flush uses async-work which must run before the
+ * next instruction, so this must be the last in the TB.
+ */
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
+ }
}
#else
static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc
b/target/ppc/translate/storage-ctrl-impl.c.inc
index 74c23a4191..b8b4454663 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -224,6 +224,13 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a,
bool local)
a->prs << TLBIE_F_PRS_SHIFT |
a->r << TLBIE_F_R_SHIFT |
local << TLBIE_F_LOCAL_SHIFT));
+ if (!local) {
+ /*
+ * Global TLB flush uses async-work which must run before the
+ * next instruction, so this must be the last in the TB.
+ */
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
+ }
return true;
#endif
--
2.43.0
- [PULL 00/72] ppc-for-9.1-1 queue, Nicholas Piggin, 2024/05/23
- [PULL 01/72] spapr: avoid overhead of finding vhyp class in critical operations, Nicholas Piggin, 2024/05/23
- [PULL 02/72] ppc/spapr: Add ibm,pi-features, Nicholas Piggin, 2024/05/23
- [PULL 03/72] target/ppc: Fix broadcast tlbie synchronisation,
Nicholas Piggin <=
- [PULL 04/72] tcg/cputlb: Remove non-synced variants of global TLB flushes, Nicholas Piggin, 2024/05/23
- [PULL 05/72] tcg/cputlb: remove other-cpu capability from TLB flushing, Nicholas Piggin, 2024/05/23
- [PULL 06/72] target/ppc: Move sync instructions to decodetree, Nicholas Piggin, 2024/05/23
- [PULL 07/72] target/ppc: Fix embedded memory barriers, Nicholas Piggin, 2024/05/23
- [PULL 08/72] target/ppc: Add ISA v3.1 variants of sync instruction, Nicholas Piggin, 2024/05/23
- [PULL 11/72] target/ppc: Move mul{li, lw, lwo, hw, hwu} instructions to decodetree., Nicholas Piggin, 2024/05/23
- [PULL 12/72] target/ppc: Make divw[u] handler method decodetree compatible., Nicholas Piggin, 2024/05/23
- [PULL 09/72] target/ppc: Merge various fpu helpers, Nicholas Piggin, 2024/05/23
- [PULL 10/72] target/ppc: Move floating-point arithmetic instructions to decodetree., Nicholas Piggin, 2024/05/23
- [PULL 14/72] target/ppc: Move neg, darn, mod{sw, uw} to decodetree., Nicholas Piggin, 2024/05/23