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Re: [RFC PATCH 03/10] target/ppc: Improve SPR indirect registers
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From: |
Nicholas Piggin |
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Subject: |
Re: [RFC PATCH 03/10] target/ppc: Improve SPR indirect registers |
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Date: |
Wed, 29 May 2024 10:13:04 +1000 |
On Tue May 28, 2024 at 4:50 PM AEST, Harsh Prateek Bora wrote:
>
> Hi Nick,
>
> On 5/26/24 17:56, Nicholas Piggin wrote:
> > SPRC/SPRD were recently added to all BookS CPUs supported, but
> > they are only tested on POWER9 and POWER10, so restrict them to
> > those CPUs.
> >
>
> Hope you mean to restrict to P9/10 for both spapr and pnv or just pnv ?
For pnv, but they are hypervisor registers so they can not be
accessed with spapr.
[...]
> > @@ -321,11 +322,25 @@ void helper_store_sprc(CPUPPCState *env, target_ulong
> > val)
> >
> > target_ulong helper_load_sprd(CPUPPCState *env)
> > {
> > + PowerPCCPU *cpu = env_archcpu(env);
> > + PnvCore *pc = pnv_cpu_state(cpu)->core;
>
> We may want to avoid creating local variable cpu here also like previous
> patches.
Since we have a maze of pointers and types, sometimes I like to
write the types down, but maybe that's just me :P
> However, is this helper meant to be accessible for spapr as well ?
Right, it's not. I *think* it should be okay to do this since it
should never be reached by spapr.
Thanks,
Nick
[RFC PATCH 05/10] ppc/pnv: Extend chip_pir class method to TIR as well, Nicholas Piggin, 2024/05/26