Re: [PATCH 2/4] target/ppc: Move VSX vector with length storage access insns to decodetree.

[Richard Henderson]

On 6/7/24 07:49, Chinmay Rath wrote:
> +static bool do_ld_st_vl(DisasContext *ctx, arg_X *a,
> +                        void (*helper)(TCGv_ptr, TCGv, TCGv_ptr, TCGv))
> +{
> +    TCGv EA;
> +    TCGv_ptr xt;
> +    if (a->rt < 32) {
> +        REQUIRE_VSX(ctx);
> +    } else {
> +        REQUIRE_VECTOR(ctx);
> +    }
> +    xt = gen_vsr_ptr(a->rt);
> +    gen_set_access_type(ctx, ACCESS_INT);
> +
> +    if (a->ra) {
> +        EA = tcg_temp_new();
> +        tcg_gen_mov_tl(EA, cpu_gpr[a->ra]);
> +    } else {
> +        EA = tcg_constant_tl(0);
> +    }
> +    if (NARROW_MODE(ctx)) {
> +        tcg_gen_ext32u_tl(EA, EA);

ra == 0, narrow mode, will crash, due to write into constant 0.
Obviously 0 does not need extending, so this could be

    if (!a->ra) {
        ea = constant 0;
    } else if (narrow mode) {
        ea = tcg_temp_new();
        tcg_gen_ext32u_tl(ea, cpu_gpr[a->ra]);
    } else {
        ra = cpu_gpr[a->ra];
    }


Aren't there existing helper functions for computing this address?
And if not, better to create one.


r~