Re: [Qemu-riscv] [PATCH v3 01/35] target/riscv: Move CPURISCVState point

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Re: [Qemu-riscv] [PATCH v3 01/35] target/riscv: Move CPURISCVState point

From:	Richard Henderson
Subject:	Re: [Qemu-riscv] [PATCH v3 01/35] target/riscv: Move CPURISCVState pointer to DisasContext
Date:	Wed, 31 Oct 2018 17:07:50 +0000
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1

On 10/31/18 1:19 PM, Bastian Koppelmann wrote:
> CPURISCVState is rarely used, so there is no need to pass it to every
> translate function. This paves the way for decodetree which only passes
> DisasContext to translate functions.
> 
> Reviewed-by: Palmer Dabbelt <address@hidden>
> Signed-off-by: Bastian Koppelmann <address@hidden>
> ---
>  target/riscv/translate.c | 15 ++++++++-------
>  1 file changed, 8 insertions(+), 7 deletions(-)

Reviewed-by: Richard Henderson <address@hidden>


r~

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Re: [Qemu-riscv] [PATCH v3 23/35] target/riscv: Remove manual decoding from gen_store(), (continued)
- [Qemu-riscv] [PATCH v3 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2018/10/31
  - Re: [Qemu-riscv] [PATCH v3 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Richard Henderson, 2018/10/31
  - Re: [Qemu-riscv] [PATCH v3 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Richard Henderson, 2018/10/31
- [Qemu-riscv] [PATCH v3 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Bastian Koppelmann, 2018/10/31
  - Re: [Qemu-riscv] [PATCH v3 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Richard Henderson, 2018/10/31
- [Qemu-riscv] [PATCH v3 11/35] target/riscv: Convert RV64A insns to decodetree, Bastian Koppelmann, 2018/10/31
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 11/35] target/riscv: Convert RV64A insns to decodetree, Alistair, 2018/10/31
- [Qemu-riscv] [PATCH v3 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 01/35] target/riscv: Move CPURISCVState pointer to DisasContext, Bastian Koppelmann, 2018/10/31
  - Re: [Qemu-riscv] [PATCH v3 01/35] target/riscv: Move CPURISCVState pointer to DisasContext, Richard Henderson <=
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 01/35] target/riscv: Move CPURISCVState pointer to DisasContext, Alistair Francis, 2018/10/31
- [Qemu-riscv] [PATCH v3 07/35] target/riscv: Convert RVXI fence insns to decodetree, Bastian Koppelmann, 2018/10/31
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 07/35] target/riscv: Convert RVXI fence insns to decodetree, Alistair, 2018/10/31
- [Qemu-riscv] [PATCH v3 05/35] target/riscv: Convert RV64I load/store insns to decodetree, Bastian Koppelmann, 2018/10/31
  - Re: [Qemu-riscv] [PATCH v3 05/35] target/riscv: Convert RV64I load/store insns to decodetree, Richard Henderson, 2018/10/31
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 05/35] target/riscv: Convert RV64I load/store insns to decodetree, Alistair, 2018/10/31
- [Qemu-riscv] [PATCH v3 16/35] target/riscv: Convert RV priv insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-riscv] [PATCH v3 26/35] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2018/10/31
  - Re: [Qemu-riscv] [PATCH v3 26/35] target/riscv: Remove shift and slt insn manual decoding, Richard Henderson, 2018/10/31
- [Qemu-riscv] [PATCH v3 28/35] target/riscv: Rename trans_arith to gen_arith, Bastian Koppelmann, 2018/10/31

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