[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 25/35] target/riscv: make ADD/SU

From: Richard Henderson
Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
Date: Wed, 31 Oct 2018 22:27:51 +0000
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1

On 10/31/18 8:44 PM, Alistair Francis wrote:
> This series causes a lot of kernel oops during boot...

The only bug I can see is in trans_addw.  But that's a biggie and could easily
explain, since non-extended values could have caused a compare to misfire.


reply via email to

[Prev in Thread] Current Thread [Next in Thread]