[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 0/5] Connect a PCIe host and gra

From: Andrea Bolognani
Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH v6 0/5] Connect a PCIe host and graphics support to RISC-V
Date: Thu, 01 Nov 2018 09:20:33 +0100

On Wed, 2018-10-31 at 13:10 -0700, Alistair Francis wrote:
> On Wed, Oct 31, 2018 at 7:51 AM Andrea Bolognani <address@hidden> wrote:
> > With the pcie.0 <- pcie-root-port <- virtio-net-pci setup I get
> > 
> >   qemu-system-riscv64: -device pcie-root-port,port=0x8,chassis=1,\
> >   id=pci.1,bus=pcie.0,multifunction=on,addr=0x1: MSI-X is not \
> >   supported by interrupt controller
> > 
> > just like last time, which as I mentioned is a problem for libvirt
> > because we follow the recommendations outlined in qemu/docs/pcie.txt
> > and never plug devices into pcie.0 directly.
> At the moment we can't support MSI, the interrupt controller doesn't
> support MSI.

I see. Are there plans for that to change? Will we eventually need
something like Arm's 'gic-version' machine option to pick a more
featureful interrupt controller?

Either way, as it is we certainly can't flip the default to
virtio-pci at the libvirt level quite yet, so we'll have to stick
with virtio-mmio for a while longer... Not exactly the outcome I
was hoping for :(

> > Let me know if you need me to try anything else :)
> Any ideas on how to debug the confusing memory mappings or
> non-existent interrupts would be helpful :)

Sorry, not really my area of expertise O:-)

Andrea Bolognani / Red Hat / Virtualization

reply via email to

[Prev in Thread] Current Thread [Next in Thread]