Re: [Qemu-riscv] [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support

[no-reply]

Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: address@hidden
Type: series
Subject: [Qemu-devel] [RFC v1 00/23]  Add RISC-V TCG backend support

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
e0946be configure: Add support for building RISC-V host
769ab2a dias: Add RISC-V support
88c2947 tcg: Add RISC-V cpu signal handler
19e47a6 riscv: tcg-target: Add the target init code
506445c riscv: tcg-target: Add the prologue generation
496bf6b riscv: tcg-target: Add the out op decoder
7d5359d riscv: tcg-target: Add direct load and store instructions
25c5371 riscv: tcg-target: Add slowpath load and store instructions
4ca5f0c riscv: tcg-target: Add branch and jump instructions
cd8821b riscv: tcg-target: Add the out load and store instructions
58bb3e0 riscv: tcg-target: Add the extract instructions
a9dc143 riscv: tcg-target: Add the mov and movi instruction
4cf20d8 riscv: tcg-target: Add the relocation functions
78c1eb9 riscv: tcg-target: Add the instruction emitters
e277371 riscv: tcg-target: Add the immediate encoders
dcdb8bc riscv: tcg-target: Add support for the constraints
6a691a5 riscv: tcg-target: Regiser the JIT
b2165c4 riscv: Add the tcg target registers
243a714 riscv: Add the tcg-target header file
c2feca77 exec: Add RISC-V GCC poison macro
19ca815 linux-user: Add host dependency for RISC-V 64-bit
e84813f linux-user: Add host dependency for RISC-V 32-bit
a62d116 elf.h: Add the RISCV ELF magic numbers

=== OUTPUT BEGIN ===
Checking PATCH 1/23: elf.h: Add the RISCV ELF magic numbers...
Checking PATCH 2/23: linux-user: Add host dependency for RISC-V 32-bit...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11: 
new file mode 100644

total: 0 errors, 1 warnings, 11 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 3/23: linux-user: Add host dependency for RISC-V 64-bit...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11: 
new file mode 100644

total: 0 errors, 1 warnings, 11 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 4/23: exec: Add RISC-V GCC poison macro...
Checking PATCH 5/23: riscv: Add the tcg-target header file...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11: 
new file mode 100644

WARNING: architecture specific defines should be avoided
#43: FILE: tcg/riscv/tcg-target.h:28:
+#if __riscv_xlen == 32

total: 0 errors, 2 warnings, 173 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 6/23: riscv: Add the tcg target registers...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#11: 
new file mode 100644

total: 0 errors, 1 warnings, 120 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 7/23: riscv: tcg-target: Regiser the JIT...
Checking PATCH 8/23: riscv: tcg-target: Add support for the constraints...
Checking PATCH 9/23: riscv: tcg-target: Add the immediate encoders...
Checking PATCH 10/23: riscv: tcg-target: Add the instruction emitters...
Checking PATCH 11/23: riscv: tcg-target: Add the relocation functions...
Checking PATCH 12/23: riscv: tcg-target: Add the mov and movi instruction...
Checking PATCH 13/23: riscv: tcg-target: Add the extract instructions...
Checking PATCH 14/23: riscv: tcg-target: Add the out load and store 
instructions...
Checking PATCH 15/23: riscv: tcg-target: Add branch and jump instructions...
Checking PATCH 16/23: riscv: tcg-target: Add slowpath load and store 
instructions...
Checking PATCH 17/23: riscv: tcg-target: Add direct load and store 
instructions...
ERROR: spaces required around that '*' (ctx:WxV)
#68: FILE: tcg/riscv/tcg-target.inc.c:1011:
+    tcg_insn_unit *label_ptr[1];
                   ^

ERROR: spaces required around that '*' (ctx:WxV)
#133: FILE: tcg/riscv/tcg-target.inc.c:1076:
+    tcg_insn_unit *label_ptr[1];
                   ^

total: 2 errors, 0 warnings, 151 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 18/23: riscv: tcg-target: Add the out op decoder...
Checking PATCH 19/23: riscv: tcg-target: Add the prologue generation...
Checking PATCH 20/23: riscv: tcg-target: Add the target init code...
Checking PATCH 21/23: tcg: Add RISC-V cpu signal handler...
Checking PATCH 22/23: dias: Add RISC-V support...
Checking PATCH 23/23: configure: Add support for building RISC-V host...
=== OUTPUT END ===

Test command exited with code: 1


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