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Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the X

From: Alistair Francis
Subject: Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
Date: Wed, 21 Nov 2018 10:32:45 -0800

On Wed, Nov 21, 2018 at 10:05 AM Logan Gunthorpe <address@hidden> wrote:
> On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> > Connect the Xilinx PCIe device based on the information in the device
> > tree stored in the ROM of the HiFish Unleashed board.
> I only briefly tested this patch but could not get any PCI devices to
> come up with the sifive_u machine. Depending on the kernel I tried, it
> either failed to initialize a Xilinx PCIe (likely due to a mismatch with
> the DT) or it appears to successfully initialize a Microsemi device but
> did not enumerate any devices underneath.

That seems like either a kernel or bbl issue.

You need to make sure that bbl doesn't edit the device tree (to add
the Microsemi device or remove the Xilinx one) and ensure your kernel
supports the Xilinx one.

> In any case, it would be nice if the Microsemi/Xilinx confusion was at
> least explained in the commit message.

What should we say? The QEMU machine accurately models the real
hardware which reports a Xilinx PCIe. The confusion generally appears
above QEMU where people are used to using the MicroSemi one.


> Thanks,
> Logan

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