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Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the X

From: Logan Gunthorpe
Subject: Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
Date: Wed, 21 Nov 2018 12:15:14 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1

On 2018-11-21 12:02 p.m., Alistair Francis wrote:
> On Wed, Nov 21, 2018 at 10:50 AM Logan Gunthorpe <address@hidden> wrote:
>> On 2018-11-21 11:32 a.m., Alistair Francis wrote:
>>> That seems like either a kernel or bbl issue.
>>> You need to make sure that bbl doesn't edit the device tree (to add
>>> the Microsemi device or remove the Xilinx one) and ensure your kernel
>>> supports the Xilinx one.
>> Ok, how do I stop bbl from editing the device tree? I have a kernel with
>> Xilinx PCI support but it fails initializing on that machine (see below).
> You should just be able to edit the source, grep for "microsemi".

I don't see any "microsemi" in my riscv-pk source...


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