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Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the X

From: Logan Gunthorpe
Subject: Re: [Qemu-riscv] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
Date: Wed, 21 Nov 2018 12:24:56 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1

On 2018-11-21 12:21 p.m., Alistair Francis wrote:
> On Wed, Nov 21, 2018 at 11:19 AM Logan Gunthorpe <address@hidden> wrote:
>> Well, I also have a kernel (one I've built myself) without microsemi
>> support, but with Xilinx support and it also doesn't work (see my dmesg
>> logs I sent).
> So this one should work.

It does not, see the dmesgs I sent a few emails ago.

>>> For people who have modified the standard bbl to edit the device tree
>>> before passing it to Linux to add the MicroSemi PCIe node, it won't
>>> work. That's a very small number of people who have modified the
>>> standard boot loader. I don't think we need to document how those
>>> people get back to the default set-up.
>> I have not done that. And it's not working for me.
> If you haven't done this then how can Linux know to probe the
> MicroSemi PCIe root complex?

Oh, well actually, in this case I was using the bbl/kernel you sent us,
so I'm not actually sure what's in it. The stuff I built myself doesn't
have any of the microsemi stuff, so it sounds like all that was a red


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