Re: [Qemu-riscv] [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Alistair Francis]

On Wed, Nov 21, 2018 at 1:37 PM Palmer Dabbelt <address@hidden> wrote:
>
> On Wed, 21 Nov 2018 11:21:40 PST (-0800), address@hidden wrote:
> > On Wed, Nov 21, 2018 at 11:19 AM Logan Gunthorpe <address@hidden> wrote:
> >>
> >>
> >>
> >> On 2018-11-21 12:16 p.m., Alistair Francis wrote:
> >> >>> Do you see the MicroSemi PCIe probe in your dmesg?
> >> >>
> >> >> I do when I have a kernel with microsemi PCI Support (specifically the
> >> >> one included in the bbl you sent us a while back).
> >> >
> >> > Yeah, so you need to make sure that doesn't happen.
> >>
> >> Well, I also have a kernel (one I've built myself) without microsemi
> >> support, but with Xilinx support and it also doesn't work (see my dmesg
> >> logs I sent).
> >
> > So this one should work.
> >
> >>
> >> > For people who have modified the standard bbl to edit the device tree
> >> > before passing it to Linux to add the MicroSemi PCIe node, it won't
> >> > work. That's a very small number of people who have modified the
> >> > standard boot loader. I don't think we need to document how those
> >> > people get back to the default set-up.
> >>
> >> I have not done that. And it's not working for me.
> >
> > If you haven't done this then how can Linux know to probe the
> > MicroSemi PCIe root complex?
>
> BBL passes this through from the FSBL, which has the DTB compiled in:
>
> https://github.com/sifive/freedom-u540-c000-bootloader/blob/master/fsbl/ux00_fsbl.dts#L405

That's fairly new though. Our boards show a Xilinx PCIe device.

Alistair