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[Qemu-riscv] [RFC v2 12/24] riscv: tcg-target: Add the extract instructi
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [RFC v2 12/24] riscv: tcg-target: Add the extract instructions |
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Date: |
Tue, 27 Nov 2018 21:08:25 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
tcg/riscv/tcg-target.inc.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index e5a07b146f..4291a00962 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -512,6 +512,40 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg rd,
}
}
+static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff);
+}
+
+static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_SLLI, ret, arg, TCG_TARGET_REG_BITS - 16);
+ tcg_out_opc_imm(s, OPC_SRLI, ret, ret, TCG_TARGET_REG_BITS - 16);
+}
+
+static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
+ tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
+}
+
+static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_SLLI, ret, arg, TCG_TARGET_REG_BITS - 8);
+ tcg_out_opc_imm(s, OPC_SRAI, ret, ret, TCG_TARGET_REG_BITS - 8);
+}
+
+static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_SLLI, ret, arg, TCG_TARGET_REG_BITS - 16);
+ tcg_out_opc_imm(s, OPC_SRAI, ret, ret, TCG_TARGET_REG_BITS - 16);
+}
+
+static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
+}
+
void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
uintptr_t addr)
{
--
2.19.1
- [Qemu-riscv] [RFC v2 06/24] riscv: Add the tcg target registers, (continued)
- [Qemu-riscv] [RFC v2 06/24] riscv: Add the tcg target registers, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 07/24] riscv: tcg-target: Add support for the constraints, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 08/24] riscv: tcg-target: Add the immediate encoders, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 10/24] riscv: tcg-target: Add the relocation functions, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 09/24] riscv: tcg-target: Add the instruction emitters, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 11/24] riscv: tcg-target: Add the mov and movi instruction, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 12/24] riscv: tcg-target: Add the extract instructions,
Alistair Francis <=
- [Qemu-riscv] [RFC v2 13/24] riscv: tcg-target: Add the out load and store instructions, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 14/24] riscv: tcg-target: Add branch and jump instructions, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 15/24] riscv: tcg-target: Add slowpath load and store instructions, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 16/24] riscv: tcg-target: Add direct load and store instructions, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 17/24] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 18/24] riscv: tcg-target: Add the prologue generation and register the JIT, Alistair Francis, 2018/11/27