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[Qemu-riscv] [PATCH 2/2] hw/riscv/sifive_u: Set 'clock-frequency' DT pro

From: Anup Patel
Subject: [Qemu-riscv] [PATCH 2/2] hw/riscv/sifive_u: Set 'clock-frequency' DT property for SiFive UART
Date: Wed, 5 Dec 2018 13:57:03 +0530

The 'clock-frequency' DT property is required by U-Boot to compute
divider value. This patch sets 'clock-frequency' DT property of
SiFive UART DT node (similar to virt machine).

Signed-off-by: Anup Patel <address@hidden>
 hw/riscv/sifive_u.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index b3a4352986..5fa666fefc 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -238,6 +238,8 @@ static void create_fdt(SiFiveUState *s, const struct 
MemmapEntry *memmap,
     qemu_fdt_setprop_cells(fdt, nodename, "reg",
         0x0, memmap[SIFIVE_U_UART0].base,
         0x0, memmap[SIFIVE_U_UART0].size);
+    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+        SIFIVE_U_CLOCK_FREQ / 2);
     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1);

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