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[Qemu-riscv] [PATCH v1 0/5] Misc RISC-V fixes

From: Alistair Francis
Subject: [Qemu-riscv] [PATCH v1 0/5] Misc RISC-V fixes
Date: Fri, 14 Dec 2018 00:18:21 +0000

This series is another go at reducing the diff between the RISC-V fork
(https://github.com/riscv/riscv-qemu/) and mainline QEMU.

This is a small series with only a handful of changes as I don't want to
have to deal with too many conflicts all at once and I don't want to
create too much conflict with the ongoing decode tree work.

Once the decode tree work goes in we can look at rebasing the changes in
the RISC-V fork that touch translate.c.

Michael Clark (4):
  RISC-V: Add hartid and \n to interrupt logging
  RISC-V: Fix CLINT timecmp low 32-bit writes
  RISC-V: Fix PLIC pending bitfield reads
  RISC-V: Enable second UART on sifive_e and sifive_u

Nathaniel Graff (1):
  sifive_uart: Implement interrupt pending register

 hw/riscv/sifive_clint.c        |  8 ++++----
 hw/riscv/sifive_e.c            |  5 ++---
 hw/riscv/sifive_plic.c         |  2 +-
 hw/riscv/sifive_u.c            |  5 ++---
 hw/riscv/sifive_uart.c         | 24 +++++++++++++++++++-----
 include/hw/riscv/sifive_uart.h |  3 +++
 target/riscv/cpu_helper.c      | 18 ++++++++++--------
 7 files changed, 41 insertions(+), 24 deletions(-)


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