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Re: [Qemu-riscv] [PATCH v2 00/23] Add RISC-V TCG backend support
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-riscv] [PATCH v2 00/23] Add RISC-V TCG backend support |
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Date: |
Wed, 19 Dec 2018 22:07:07 -0800 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.3.1 |
On 12/19/18 11:16 AM, Alistair Francis wrote:
> This patch set adds RISC-V backend support to QEMU. This is based on
> Michael Clark's original work with extra work on top.
>
> This has been somewhat tested and can run other architecture softmmu
> code. It seems that any complex OS will eventually hang, but we can
> run the BIOS and OS startup code for a number of different operating
> systems.
>
> I haven't tested linux user support at all yet. I think Michael had that
> working reliably though and hopefully my changes haven't broken it.
>
> There are still some todos in the code (there are missing instructions
> and byte swapping) but these should assert instead of generating invalid
> code.
Queued to tcg-next, with the extrh fix.
Some of those todos are no longer todos, since e.g. bswap is now optional.
Those asserts should never fire (as a good assert should do, I suppose).
The missing instructions are only for riscv32, which afaik is just now making
its way to glibc. So a chroot complete enough to build qemu is a ways away.
I'm ok with leaving that incomplete for now.
r~
- [Qemu-riscv] [PATCH v2 15/23] riscv: tcg-target: Add branch and jump instructions, (continued)
- [Qemu-riscv] [PATCH v2 15/23] riscv: tcg-target: Add branch and jump instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 16/23] riscv: tcg-target: Add slowpath load and store instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 17/23] riscv: tcg-target: Add direct load and store instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 18/23] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 19/23] riscv: tcg-target: Add the prologue generation and register the JIT, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 20/23] riscv: tcg-target: Add the target init code, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 21/23] tcg: Add RISC-V cpu signal handler, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 23/23] configure: Add support for building RISC-V host, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 22/23] dias: Add RISC-V support, Alistair Francis, 2018/12/19
- Re: [Qemu-riscv] [PATCH v2 00/23] Add RISC-V TCG backend support,
Richard Henderson <=
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 00/23] Add RISC-V TCG backend support, no-reply, 2018/12/25