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Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to Dis
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext |
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Date: |
Wed, 16 Jan 2019 09:23:59 +1100 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 |
On 1/15/19 10:58 AM, Alistair Francis wrote:
> -static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState
> *cs)
> +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState
> *cpu)
Why change this? I know there is variation in the naming, but my
preferred default mapping is CPUState *cs, RISCVCPU *cpu.
Otherwise,
Reviewed-by: Richard Henderson <address@hidden>
r~
[Qemu-riscv] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers, Alistair Francis, 2019/01/14
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers, Richard Henderson, 2019/01/15
[Qemu-riscv] [PATCH v1 6/8] RISC-V: Add misa to DisasContext, Alistair Francis, 2019/01/14