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[Qemu-riscv] [PULL 11/11] riscv: Ensure the kernel start address is corr
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 11/11] riscv: Ensure the kernel start address is correctly cast |
Date: |
Wed, 13 Feb 2019 07:44:50 -0800 |
From: Alistair Francis <address@hidden>
Cast the kernel start address to the target bit length.
This ensures that we calculate the initrd offset to a valid address for
the architecture.
Steps to reproduce the original problem (reported by Alex):
Build U-Boot for the virt machine for riscv32. Then run it with
$ qemu-system-riscv32 -M virt -kernel u-boot -nographic -initrd <a file>
You can find the initrd address with
U-Boot# fdt addr $fdtcontroladdr
U-Boot# fdt ls /chosen
Then take a peek at that address:
U-Boot# md.b <addr>
and you will see that there is nothing there without this patch. The
reason is that the binary was loaded to a negative address.
Signed-off-by: Alistair Francis <address@hidden>
Suggested-by: Alexander Graf <address@hidden>
Reported-by: Alexander Graf <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c | 2 +-
hw/riscv/virt.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index bfc086609cb9..b1cd11363c93 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -74,7 +74,7 @@ static const struct MemmapEntry {
[SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
};
-static uint64_t load_kernel(const char *kernel_filename)
+static target_ulong load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 2730b25b6032..7bc25820feaa 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -65,7 +65,7 @@ static const struct MemmapEntry {
#define GEM_REVISION 0x10070109
-static uint64_t load_kernel(const char *kernel_filename)
+static target_ulong load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index c66ffc50cc74..2a000a58009a 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -53,7 +53,7 @@ static const struct MemmapEntry {
[SPIKE_DRAM] = { 0x80000000, 0x0 },
};
-static uint64_t load_kernel(const char *kernel_filename)
+static target_ulong load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 3e8b19c66898..fc4c6b306e13 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -62,7 +62,7 @@ static const struct MemmapEntry {
[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
};
-static uint64_t load_kernel(const char *kernel_filename)
+static target_ulong load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
--
2.18.1
- [Qemu-riscv] [PULL] RISC-V Patches for the 4.0 Soft Freeze, Part 1, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 02/11] RISC-V: Mark mstatus.fs dirty, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 01/11] RISC-V: Split out mstatus_fs from tb_flags, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 04/11] RISC-V: Use riscv prefix consistently on cpu helpers, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 05/11] RISC-V: Add priv_ver to DisasContext, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 11/11] riscv: Ensure the kernel start address is correctly cast,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 09/11] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 08/11] RISC-V: Add misa runtime write support, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 10/11] target/riscv: fix counter-enable checks in ctr(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 03/11] RISC-V: Implement mstatus.TSR/TW/TVM, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 06/11] RISC-V: Add misa to DisasContext, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PULL 07/11] RISC-V: Add misa.MAFD checks to translate, Palmer Dabbelt, 2019/02/13
- Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.0 Soft Freeze, Part 1, Peter Maydell, 2019/02/14