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[Qemu-riscv] [PATCH v7 00/35] target/riscv: Convert to decodetree

From: Palmer Dabbelt
Subject: [Qemu-riscv] [PATCH v7 00/35] target/riscv: Convert to decodetree
Date: Wed, 13 Feb 2019 07:53:39 -0800

Palmer: I caused some merge conflicts in Bastian's patch set so I
figured I'd attempt to clean these up.  As far as I'm concerned v6 was
good to go, but since the merge conflicts were fairly extensive (if
somewhat mechanical) I'd like to pass the baton back to Bastian here for
at least a sanity check.


this patchset converts the RISC-V decoder to decodetree in four major steps:

1) Convert 32-bit instructions to decodetree [Patch 1-16]:
    Many of the gen_* functions are called by the decode functions for 16-bit
    and 32-bit functions. If we move translation code from the gen_*
    functions to the generated trans_* functions of decode-tree, we get a lot of
    duplication. Therefore, we mostly generate calls to the old gen_* function
    which are properly replaced after step 2).

    Each of the trans_ functions are grouped into files corresponding to their
    ISA extension, e.g. addi which is in RV32I is translated in the file

2) Convert 16-bit instructions to decodetree [Patch 17-19]:
    All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
    we convert the arguments in the 16 bit trans_ function to the arguments of
    the corresponding 32 bit instruction and call the 32 bit trans_ function.

3) Remove old manual decoding in gen_* function [Patch 20-30]:
    this move all manual translation code into the trans_* instructions of
    decode tree, such that we can remove the old decode_* functions.

4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
   by Richard. [Patch 31-35]

full tree available at


v6 -> v7:
    - Rebased on top of riscv-for-master-4.0-sf1, which contains a
      refactoring of the original translation code.
    - Added handling of mstatus.fs to the floating-point routines.

v5 -> v6:
    - fixed funky indentation

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