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Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to
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Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree |
Date: |
Wed, 27 Feb 2019 11:19:53 -0800 (PST) |
Patchew URL: https://patchew.org/QEMU/address@hidden/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: address@hidden
Subject: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/address@hidden -> patchew/address@hidden
Switched to a new branch 'test'
5151e227ca target/riscv: Remaining rvc insn reuse 32 bit translators
ab29232b07 target/riscv: Splice remaining compressed insn pairs for riscv32 vs
riscv64
574a876a74 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
1cd5ba7c9d target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
1fee8e7fd2 target/riscv: Convert @cs_2 insns to share translation functions
3580ae8151 target/riscv: Remove decode_RV32_64G()
3794409d29 target/riscv: Remove gen_system()
f5781a75a0 target/riscv: Rename trans_arith to gen_arith
e94963588c target/riscv: Remove manual decoding of RV32/64M insn
06881e800c target/riscv: Remove shift and slt insn manual decoding
82a7df5c19 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
a4e3383293 target/riscv: Move gen_arith_imm() decoding into trans_* functions
fd78f76f5d target/riscv: Remove manual decoding from gen_store()
ffe7f21c63 target/riscv: Remove manual decoding from gen_load()
524109932e target/riscv: Remove manual decoding from gen_branch()
2ecee20041 target/riscv: Remove gen_jalr()
42e5d8cc41 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
a04293c3d8 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
edfb43ad65 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
ceef6fd959 target/riscv: Convert RV priv insns to decodetree
7ebb8921af target/riscv: Convert RV64D insns to decodetree
eea48fec16 target/riscv: Convert RV32D insns to decodetree
43a8ecfb50 target/riscv: Convert RV64F insns to decodetree
cb07a6f179 target/riscv: Convert RV32F insns to decodetree
52a7560c45 target/riscv: Convert RV64A insns to decodetree
67af82888e target/riscv: Convert RV32A insns to decodetree
2ee948d423 target/riscv: Convert RVXM insns to decodetree
d31956cb65 target/riscv: Convert RVXI csr insns to decodetree
8899edc648 target/riscv: Convert RVXI fence insns to decodetree
f909ec4291 target/riscv: Convert RVXI arithmetic insns to decodetree
4b0cf0d671 target/riscv: Convert RV64I load/store insns to decodetree
7ffa0b6fee target/riscv: Convert RV32I load/store insns to decodetree
137f154684 target/riscv: Convert RVXI branch insns to decodetree
6df0248170 target/riscv: Activate decodetree and implemnt LUI & AUIPC
=== OUTPUT BEGIN ===
1/34 Checking commit 6df024817084 (target/riscv: Activate decodetree and
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1884:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 1/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/34 Checking commit 137f1546842d (target/riscv: Convert RVXI branch insns to
decodetree)
3/34 Checking commit 7ffa0b6feeba (target/riscv: Convert RV32I load/store insns
to decodetree)
4/34 Checking commit 4b0cf0d671ea (target/riscv: Convert RV64I load/store insns
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 4/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/34 Checking commit f909ec429144 (target/riscv: Convert RVXI arithmetic insns
to decodetree)
6/34 Checking commit 8899edc64836 (target/riscv: Convert RVXI fence insns to
decodetree)
7/34 Checking commit d31956cb658a (target/riscv: Convert RVXI csr insns to
decodetree)
8/34 Checking commit 2ee948d4232d (target/riscv: Convert RVXM insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 169 lines checked
Patch 8/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/34 Checking commit 67af82888e6a (target/riscv: Convert RV32A insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 199 lines checked
Patch 9/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/34 Checking commit 52a7560c4520 (target/riscv: Convert RV64A insns to
decodetree)
11/34 Checking commit cb07a6f17966 (target/riscv: Convert RV32F insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 442 lines checked
Patch 11/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
12/34 Checking commit 43a8ecfb5028 (target/riscv: Convert RV64F insns to
decodetree)
13/34 Checking commit eea48fec1653 (target/riscv: Convert RV32D insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 398 lines checked
Patch 13/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
14/34 Checking commit 7ebb8921af68 (target/riscv: Convert RV64D insns to
decodetree)
15/34 Checking commit ceef6fd9591f (target/riscv: Convert RV priv insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 15/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
16/34 Checking commit edfb43ad6505 (target/riscv: Convert quadrant 0 of RVXC
insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#251: FILE: target/riscv/translate.c:1072:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 231 lines checked
Patch 16/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/34 Checking commit a04293c3d834 (target/riscv: Convert quadrant 1 of RVXC
insns to decodetree)
18/34 Checking commit 42e5d8cc4162 (target/riscv: Convert quadrant 2 of RVXC
insns to decodetree)
19/34 Checking commit 2ecee2004173 (target/riscv: Remove gen_jalr())
20/34 Checking commit 524109932ec8 (target/riscv: Remove manual decoding from
gen_branch())
21/34 Checking commit ffe7f21c63ef (target/riscv: Remove manual decoding from
gen_load())
22/34 Checking commit fd78f76f5ded (target/riscv: Remove manual decoding from
gen_store())
23/34 Checking commit a4e338329341 (target/riscv: Move gen_arith_imm() decoding
into trans_* functions)
24/34 Checking commit 82a7df5c19c7 (target/riscv: make ADD/SUB/OR/XOR/AND insn
use arg lists)
25/34 Checking commit 06881e800c4c (target/riscv: Remove shift and slt insn
manual decoding)
26/34 Checking commit e94963588c2c (target/riscv: Remove manual decoding of
RV32/64M insn)
27/34 Checking commit f5781a75a00d (target/riscv: Rename trans_arith to
gen_arith)
28/34 Checking commit 3794409d292a (target/riscv: Remove gen_system())
29/34 Checking commit 3580ae81511d (target/riscv: Remove decode_RV32_64G())
30/34 Checking commit 1fee8e7fd29c (target/riscv: Convert @cs_2 insns to share
translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:548:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 30/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
31/34 Checking commit 1cd5ba7c9d3e (target/riscv: Convert @cl_d, @cl_w, @cs_d,
@cs_w insns)
32/34 Checking commit 574a876a748c (target/riscv: Splice fsw_sd and flw_ld for
riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 309 lines checked
Patch 32/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
33/34 Checking commit ab29232b0705 (target/riscv: Splice remaining compressed
insn pairs for riscv32 vs riscv64)
34/34 Checking commit 5151e227ca32 (target/riscv: Remaining rvc insn reuse 32
bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to address@hidden
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, (continued)
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, Alistair Francis, 2019/02/22
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
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- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree,
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- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27