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[Qemu-riscv] [PATCH v1 09/12] RISC-V: Convert trap debugging to trace ev
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v1 09/12] RISC-V: Convert trap debugging to trace events |
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Date: |
Sat, 16 Mar 2019 01:21:12 +0000 |
From: Michael Clark <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
---
Makefile.objs | 1 +
target/riscv/cpu_helper.c | 12 +++---------
target/riscv/trace-events | 2 ++
3 files changed, 6 insertions(+), 9 deletions(-)
create mode 100644 target/riscv/trace-events
diff --git a/Makefile.objs b/Makefile.objs
index 72debbf5c5..cf065de5ed 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -186,6 +186,7 @@ trace-events-subdirs += target/hppa
trace-events-subdirs += target/i386
trace-events-subdirs += target/mips
trace-events-subdirs += target/ppc
+trace-events-subdirs += target/riscv
trace-events-subdirs += target/s390x
trace-events-subdirs += target/sparc
trace-events-subdirs += ui
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index a02f4dad8c..6d3fbc3401 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -22,8 +22,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
-
-#define RISCV_DEBUG_INTERRUPT 0
+#include "trace.h"
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
{
@@ -493,13 +492,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
}
}
- if (RISCV_DEBUG_INTERRUPT) {
- qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": %s %s, "
- "epc 0x" TARGET_FMT_lx ": tval 0x" TARGET_FMT_lx "\n",
- env->mhartid, async ? "intr" : "trap",
- (async ? riscv_intr_names : riscv_excp_names)[cause],
- env->pc, tval);
- }
+ trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 16 ?
+ (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)");
if (env->priv <= PRV_S &&
cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
diff --git a/target/riscv/trace-events b/target/riscv/trace-events
new file mode 100644
index 0000000000..48af0373df
--- /dev/null
+++ b/target/riscv/trace-events
@@ -0,0 +1,2 @@
+# target/riscv/cpu_helper.c
+riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t
tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64",
epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s"
--
2.21.0
- [Qemu-riscv] [PATCH v1 00/12] Upstream RISC-V fork patches, part 4, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 11/12] riscv: sifive_u: Allow up to 4 CPUs to be created, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 12/12] target/riscv: Remove unused struct, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 10/12] RISC-V: Update load reservation comment in do_interrupt, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 07/12] RISC-V: Change local interrupts from edge to level, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 09/12] RISC-V: Convert trap debugging to trace events,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 08/12] RISC-V: Add support for vectored interrupts, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 06/12] RISC-V: linux-user support for RVE ABI, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 05/12] elf: Add RISC-V PSABI ELF header defines, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 03/12] RISC-V: Allow interrupt controllers to claim interrupts, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 01/12] riscv: pmp: Log pmp access errors as guest errors, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 04/12] RISC-V: Remove unnecessary disassembler constraints, Alistair Francis, 2019/03/15
- [Qemu-riscv] [PATCH v1 02/12] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC, Alistair Francis, 2019/03/15