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Re: [Qemu-riscv] [PATCH for-4.1 4/8] target/riscv: Merge argument decode
From: |
Richard Henderson |
Subject: |
Re: [Qemu-riscv] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti |
Date: |
Thu, 25 Apr 2019 09:50:41 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 |
On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
>> # *** RV64C Standard Extension (Quadrant 2) ***
>> -c_slli 000 . ..... ..... 10 @c_shift2
>> +slli 000 . ..... ..... 10 @c_shift2
>
> This is another one where rd=0 is illegal in the compressed ISA, but again we
> don't appear to handle these correctly before the cleanups.
I see "HINT, rd=0" in the 2.2 documentation for this case.
r~