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Re: [Qemu-riscv] [PATCH for 4.1] target/riscv: Only flush TLB if SATP.AS


From: Jonathan Behrens
Subject: Re: [Qemu-riscv] [PATCH for 4.1] target/riscv: Only flush TLB if SATP.ASID changes
Date: Mon, 6 May 2019 11:49:36 -0400

Argh, meant to include a signed off by line:

Signed-off-by: Jonathan Behrens <address@hidden>

On Mon, May 6, 2019 at 11:31 AM Jonathan Behrens <address@hidden> wrote:
There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857
---
 target/riscv/csr.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6083c782a1..1ec1222da1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -732,7 +732,9 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
             return -1;
         } else {
-            tlb_flush(CPU(riscv_env_get_cpu(env)));
+            if((val ^ env->satp) & SATP_ASID) {
+                tlb_flush(CPU(riscv_env_get_cpu(env)));
+            }
             env->satp = val;
         }
     }
--
2.20.1


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