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[Qemu-riscv] [RFC v1 14/23] riscv: plic: Remove unused interrupt functio
From: |
Alistair Francis |
Subject: |
[Qemu-riscv] [RFC v1 14/23] riscv: plic: Remove unused interrupt functions |
Date: |
Fri, 24 May 2019 16:46:12 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
hw/riscv/sifive_plic.c | 12 ------------
include/hw/riscv/sifive_plic.h | 3 ---
2 files changed, 15 deletions(-)
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index 07a032d93d..1e7e4c8d51 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -159,18 +159,6 @@ static void sifive_plic_update(SiFivePLICState *plic)
}
}
-void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq)
-{
- sifive_plic_set_pending(plic, irq, true);
- sifive_plic_update(plic);
-}
-
-void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq)
-{
- sifive_plic_set_pending(plic, irq, false);
- sifive_plic_update(plic);
-}
-
static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
{
int i, j;
diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h
index ce8907f6aa..3b8a623919 100644
--- a/include/hw/riscv/sifive_plic.h
+++ b/include/hw/riscv/sifive_plic.h
@@ -69,9 +69,6 @@ typedef struct SiFivePLICState {
uint32_t aperture_size;
} SiFivePLICState;
-void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq);
-void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq);
-
DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
uint32_t num_sources, uint32_t num_priorities,
uint32_t priority_base, uint32_t pending_base,
--
2.21.0
- [Qemu-riscv] [RFC v1 00/23] Add RISC-V Hypervisor Extension, Alistair Francis, 2019/05/24
- Re: [Qemu-riscv] [RFC v1 00/23] Add RISC-V Hypervisor Extension, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 23/23] target/riscv: Allow enabling the Hypervisor extension, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 22/23] target/riscv: Call the second stage MMU in virtualisation mode, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 21/23] target/riscv: Implement second stage MMU, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 20/23] target/riscv: Allow specifying number of MMU stages, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 19/23] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 18/23] target/riscv: Add hfence instructions, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 17/23] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 15/23] riscv: plic: Always set sip.SEIP bit for HS, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 14/23] riscv: plic: Remove unused interrupt functions,
Alistair Francis <=
- [Qemu-riscv] [RFC v1 13/23] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 16/23] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 10/23] target/riscv: Add background CSRs accesses, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 09/23] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 08/23] target/riscv: Add support for background interrupt setting, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 04/23] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 12/23] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 11/23] target/riscv: Add background register swapping function, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 06/23] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/05/24
- [Qemu-riscv] [RFC v1 01/23] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/05/24