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[Qemu-riscv] [PULL 27/29] target/riscv: Add checks for several RVC reser
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 27/29] target/riscv: Add checks for several RVC reserved operands |
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Date: |
Sat, 25 May 2019 18:09:46 -0700 |
From: Richard Henderson <address@hidden>
C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved
operands that were not diagnosed.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/insn16-64.decode | 10 ++++++++--
target/riscv/insn16.decode | 7 ++++++-
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
index 055859d29f61..672e1e916f6b 100644
--- a/target/riscv/insn16-64.decode
+++ b/target/riscv/insn16-64.decode
@@ -21,10 +21,16 @@ ld 011 ... ... .. ... 00 @cl_d
sd 111 ... ... .. ... 00 @cs_d
# *** RV64C Standard Extension (Quadrant 1) ***
-addiw 001 . ..... ..... 01 @ci
+{
+ illegal 001 - 00000 ----- 01 # c.addiw, RES rd=0
+ addiw 001 . ..... ..... 01 @ci
+}
subw 100 1 11 ... 00 ... 01 @cs_2
addw 100 1 11 ... 01 ... 01 @cs_2
# *** RV64C Standard Extension (Quadrant 2) ***
-ld 011 . ..... ..... 10 @c_ldsp
+{
+ illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0
+ ld 011 . ..... ..... 10 @c_ldsp
+}
sd 111 . ..... ..... 10 @c_sdsp
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 433c0e8c6861..1cb93876fe0f 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -96,6 +96,7 @@ sw 110 ... ... .. ... 00 @cs_w
addi 000 . ..... ..... 01 @ci
addi 010 . ..... ..... 01 @c_li
{
+ illegal 011 0 ----- 00000 01 # c.addi16sp and c.lui, RES nzimm=0
addi 011 . 00010 ..... 01 @c_addi16sp
lui 011 . ..... ..... 01 @c_lui
}
@@ -113,8 +114,12 @@ bne 111 ... ... ..... 01 @cb_z
# *** RV32/64C Standard Extension (Quadrant 2) ***
slli 000 . ..... ..... 10 @c_shift2
fld 001 . ..... ..... 10 @c_ldsp
-lw 010 . ..... ..... 10 @c_lwsp
{
+ illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0
+ lw 010 . ..... ..... 10 @c_lwsp
+}
+{
+ illegal 100 0 00000 00000 10 # c.jr, RES rs1=0
jalr 100 0 ..... 00000 10 @c_jalr rd=0 # C.JR
addi 100 0 ..... ..... 10 @c_mv
}
--
2.21.0
- [Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 28/29] target/riscv: More accurate handling of `sip` CSR, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 29/29] target/riscv: Only flush TLB if SATP.ASID changes, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 27/29] target/riscv: Add checks for several RVC reserved operands,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 25/29] target/riscv: Add the HSTATUS register masks, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 26/29] target/riscv: Add the HGATP register masks, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 24/29] target/riscv: Add Hypervisor CSR macros, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 20/29] target/riscv: Trigger interrupt on MIP update asynchronously, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 23/29] target/riscv: Allow setting mstatus virtulisation bits, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 17/29] target/riscv: Deprecate the generic no MMU CPUs, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 16/29] target/riscv: Add a base 32 and 64 bit CPU, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 15/29] target/riscv: Create settable CPU properties, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 11/29] target/riscv: Remove spaces from register names, Palmer Dabbelt, 2019/05/25
- [Qemu-riscv] [PULL 08/29] target/riscv: Use pattern groups in insn16.decode, Palmer Dabbelt, 2019/05/25