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[Qemu-riscv] [PATCH v1 01/27] target/riscv: Don't set write permissions
From: |
Alistair Francis |
Subject: |
[Qemu-riscv] [PATCH v1 01/27] target/riscv: Don't set write permissions on dirty PTEs |
Date: |
Fri, 7 Jun 2019 14:55:21 -0700 |
Setting write permission on dirty PTEs results in userspace inside a
Hypervisor guest (VU) becoming corrupted. This appears to be becuase it
ends up with write permission in the second stage translation in cases
where we aren't doing a store.
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_helper.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b1bee3d45d..872835177a 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -326,10 +326,8 @@ restart:
if ((pte & PTE_X)) {
*prot |= PAGE_EXEC;
}
- /* add write permission on stores or if the page is already dirty,
- so that we TLB miss on later writes to update the dirty bit */
- if ((pte & PTE_W) &&
- (access_type == MMU_DATA_STORE || (pte & PTE_D))) {
+ /* add write permission on stores */
+ if ((pte & PTE_W) && (access_type == MMU_DATA_STORE)) {
*prot |= PAGE_WRITE;
}
return TRANSLATE_SUCCESS;
--
2.21.0
- [Qemu-riscv] [PATCH v1 00/27] Add RISC-V Hypervisor Extension, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 02/27] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 05/27] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 03/27] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 01/27] target/riscv: Don't set write permissions on dirty PTEs,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 07/27] target/riscv: Remove strict perm checking for CSR R/W, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 04/27] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 06/27] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 08/27] target/riscv: Create function to test if FP is enabled, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 09/27] target/riscv: Add support for background interrupt setting, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 10/27] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 12/27] target/riscv: Add background register swapping function, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 13/27] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 16/27] riscv: plic: Always set sip.SEIP bit for HS, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 11/27] target/riscv: Add background CSRs accesses, Alistair Francis, 2019/06/07