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[Qemu-riscv] [PATCH v1 24/27] target/riscv: Allow specifying number of M
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v1 24/27] target/riscv: Allow specifying number of MMU stages |
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Date: |
Fri, 7 Jun 2019 14:56:36 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_helper.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 6cef78a2c7..6ff4272da2 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -286,7 +286,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong
newpriv)
static int get_physical_address(CPURISCVState *env, hwaddr *physical,
int *prot, target_ulong addr,
int access_type, int mmu_idx,
- bool first_stage)
+ bool first_stage, bool two_stage)
{
/* NOTE: the env->pc value visible here will not be
* correct, but the value visible to the exception handler
@@ -518,9 +518,10 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr
addr)
int mmu_idx = cpu_mmu_index(&cpu->env, false);
if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx,
- true)) {
+ true, false)) {
return -1;
}
+
return phys_addr;
}
@@ -579,7 +580,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
__func__, address, access_type, mmu_idx);
ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx,
- true);
+ true, false);
qemu_log_mask(CPU_LOG_MMU,
"%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
--
2.21.0
- [Qemu-riscv] [PATCH v1 11/27] target/riscv: Add background CSRs accesses, (continued)
- [Qemu-riscv] [PATCH v1 11/27] target/riscv: Add background CSRs accesses, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 15/27] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 17/27] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 18/27] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 14/27] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 19/27] target/riscv: Add hfence instructions, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 22/27] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 21/27] target/riscv: Mark both sstatus and bsstatus as dirty, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 23/27] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 25/27] target/riscv: Implement second stage MMU, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 24/27] target/riscv: Allow specifying number of MMU stages,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 20/27] target/riscv: Disable guest FP support based on backgrond status, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 27/27] target/riscv: Allow enabling the Hypervisor extension, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 26/27] target/riscv: Call the second stage MMU in virtualisation mode, Alistair Francis, 2019/06/07