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[Qemu-riscv] TLB refresh issue

From: Quentin Mundell
Subject: [Qemu-riscv] TLB refresh issue
Date: Wed, 19 Jun 2019 15:33:13 +0000


I have updated my QEMU version (from 3.x to today's master).
I now get all sort of weird and not easily reproducible exceptions triggered in my risc-v guest, happening from both user and supervisor mode.

The command I use is roughly `qemu-system-riscv64 -machine sifive_u -m 1024 -kernel mybinary.elf` (sorry, I cannot share the elf).

I have bisected this issue back to commit c7b95171881569284501ed01fec7acb8654db7b.
Some TLB flushes were removed in the following places:
target/riscv/cpu_helper.c: `csr_write_helper(env, s, CSR_MSTATUS);` -> `env->mstatus = s;` (twice)
target/riscv/op_helper.c: `csr_write_helper(env, s, CSR_MSTATUS);` -> `env->mstatus = s;` (twice)
These are the places where the privileged mode is switched.

If I add them back (`tlb_flush(env_cpu(env));`), everything is fine again.

However, in the `riscv_cpu_set_mode` function, I see the following comment:
> tlb_flush is unnecessary as mode is contained in mmu_idx
It would suggest adding back TLB flushes is not the way to go...

Does someone with better knowledge of the codebase can tell me how to proceed here?
- Should I submit a patch adding back the TLB flushes?
- Is it an issue somewhere else?


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