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[Qemu-riscv] [PATCH v1 2/5] hw/riscv: Add support for loading a firmware
From: |
Alistair Francis |
Subject: |
[Qemu-riscv] [PATCH v1 2/5] hw/riscv: Add support for loading a firmware |
Date: |
Mon, 24 Jun 2019 15:11:52 -0700 |
Add support for loading a firmware file for the virt machine and the
SiFive U. This can be run with the following command:
qemu-system-riscv64 -machine virt -bios fw_jump.bin -kernel vmlinux
Signed-off-by: Alistair Francis <address@hidden>
---
hw/riscv/boot.c | 26 ++++++++++++++++++++++++++
hw/riscv/sifive_u.c | 4 ++++
hw/riscv/virt.c | 4 ++++
include/hw/riscv/boot.h | 2 ++
4 files changed, 36 insertions(+)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 0c8e72e455..883df49a0c 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -23,8 +23,34 @@
#include "exec/cpu-defs.h"
#include "hw/loader.h"
#include "hw/riscv/boot.h"
+#include "hw/boards.h"
#include "elf.h"
+#if defined(TARGET_RISCV32)
+# define KERNEL_BOOT_ADDRESS 0x80400000
+#else
+# define KERNEL_BOOT_ADDRESS 0x80200000
+#endif
+
+target_ulong riscv_load_firmware(const char *firmware_filename,
+ hwaddr firmware_load_addr)
+{
+ uint64_t firmware_entry, firmware_start, firmware_end;
+
+ if (load_elf(firmware_filename, NULL, NULL, NULL, &firmware_entry,
+ &firmware_start, &firmware_end, 0, EM_RISCV, 1, 0) > 0) {
+ return firmware_entry;
+ }
+
+ if (load_image_targphys_as(firmware_filename, firmware_load_addr,
+ ram_size, NULL) > 0) {
+ return firmware_load_addr;
+ }
+
+ error_report("could not load firmware '%s'", firmware_filename);
+ exit(1);
+}
+
target_ulong riscv_load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 1b9281bd4a..a04f2d0754 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -266,6 +266,10 @@ static void riscv_sifive_u_init(MachineState *machine)
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
+ if (machine->firmware) {
+ riscv_load_firmware(machine->firmware, memmap[SIFIVE_U_DRAM].base);
+ }
+
if (machine->kernel_filename) {
riscv_load_kernel(machine->kernel_filename);
}
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 5f8c11471b..7fcc8c03b5 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -380,6 +380,10 @@ static void riscv_virt_board_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
mask_rom);
+ if (machine->firmware) {
+ riscv_load_firmware(machine->firmware, memmap[VIRT_DRAM].base);
+ }
+
if (machine->kernel_filename) {
uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index f84fd6c2df..daa179b600 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -20,6 +20,8 @@
#ifndef RISCV_BOOT_H
#define RISCV_BOOT_H
+target_ulong riscv_load_firmware(const char *firmware_filename,
+ hwaddr firmware_load_addr);
target_ulong riscv_load_kernel(const char *kernel_filename);
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
uint64_t kernel_entry, hwaddr *start);
--
2.22.0
- [Qemu-riscv] [PATCH v1 0/5] RISC-V: Add firmware loading support and default, Alistair Francis, 2019/06/24
- [Qemu-riscv] [PATCH v1 1/5] hw/riscv: Split out the boot functions, Alistair Francis, 2019/06/24
- [Qemu-riscv] [PATCH v1 3/5] hw/riscv: Extend the kernel loading support, Alistair Francis, 2019/06/24
- [Qemu-riscv] [PATCH v1 2/5] hw/riscv: Add support for loading a firmware,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 5/5] hw/riscv: Load OpenSBI as the default firmware, Alistair Francis, 2019/06/24
- [Qemu-riscv] [PATCH v1 4/5] roms: Add OpenSBI version 0.3, Alistair Francis, 2019/06/24
- Re: [Qemu-riscv] [PATCH v1 0/5] RISC-V: Add firmware loading support and default, Alistair Francis, 2019/06/25