[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-riscv] [Qemu-devel] [PATCH] atomic failures on qemu-system-ris

From: Palmer Dabbelt
Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
Date: Wed, 26 Jun 2019 01:25:40 -0700 (PDT)

On Wed, 26 Jun 2019 00:48:51 PDT (-0700), address@hidden wrote:
On 6/26/19 8:07 AM, Palmer Dabbelt wrote:
On Tue, 25 Jun 2019 08:36:28 PDT (-0700), address@hidden wrote:
On 6/24/19 8:08 PM, Joel Sing wrote:
Regarding the alignment for reservations, the
specification does require this, although I do not recall seeing any
of this by qemu itself.

Ah, I see it now.  Enforcement begins here:

static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
    REQUIRE_EXT(ctx, RVA);
    return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));

This will force softmmu (but notably not linux-user; a design limitation) to
generate an alignment fault for an unaligned address.

That was probably correct at the time the code went in, as the ISA used to
allow these to succeed but not be atomic.  No implementations did this, so as
part of the ratification process we just mandated that unaligned atomics always

Is there a better way to fix this than just doing the alignment check

You misunderstand.  The code is exactly correct as-is.  The alignment check
happens implicitly as a part of the softmmu tlb resolution.

Sorry, I thought you said it wasn't happening for linux-user?  If it happens
for both then we're good.

reply via email to

[Prev in Thread] Current Thread [Next in Thread]