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Re: [Qemu-riscv] [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
Tue, 2 Jul 2019 09:26:26 +0800
On Tue, Jul 2, 2019 at 8:20 AM Alistair Francis <address@hidden> wrote:
> On Mon, Jul 1, 2019 at 8:56 AM <address@hidden> wrote:
> > From: Jonathan Behrens <address@hidden>
> > QEMU currently always triggers an illegal instruction exception when
> > code attempts to read the time CSR. This is valid behavor, but only if
> > the TM bit in mcounteren is hardwired to zero. This change also
> > corrects mcounteren and scounteren CSRs to be 32-bits on both 32-bit
> > and 64-bit targets.
> > Signed-off-by: Jonathan Behrens <address@hidden>
> Reviewed-by: Alistair Francis <address@hidden>
I am a little bit lost here. I think we agreed to allow directly read
to time CSR when mcounteren.TM is set, no?