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Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 09/15] cputlb: Access MemoryRegi
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 09/15] cputlb: Access MemoryRegion with MemOp |
Date: |
Thu, 25 Jul 2019 13:49:11 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 |
On 7/25/19 1:38 PM, Philippe Mathieu-Daudé wrote:
> On 7/25/19 11:55 AM, address@hidden wrote:
>> Signed-off-by: Tony Nguyen <address@hidden>
>> ---
>> accel/tcg/cputlb.c | 8 ++++----
>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
>> index 523be4c..a4a0bf7 100644
>> --- a/accel/tcg/cputlb.c
>> +++ b/accel/tcg/cputlb.c
>> @@ -906,8 +906,8 @@ static uint64_t io_readx(CPUArchState *env,
>> CPUIOTLBEntry *iotlbentry,
>> qemu_mutex_lock_iothread();
>> locked = true;
>> }
>> - r = memory_region_dispatch_read(mr, mr_offset,
>> - &val, size, iotlbentry->attrs);
>> + r = memory_region_dispatch_read(mr, mr_offset, &val, SIZE_MEMOP(size),
>> + iotlbentry->attrs);
>> if (r != MEMTX_OK) {
>> hwaddr physaddr = mr_offset +
>> section->offset_within_address_space -
>> @@ -947,8 +947,8 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry
>> *iotlbentry,
>> qemu_mutex_lock_iothread();
>> locked = true;
>> }
>> - r = memory_region_dispatch_write(mr, mr_offset,
>> - val, size, iotlbentry->attrs);
>> + r = memory_region_dispatch_write(mr, mr_offset, val, SIZE_MEMOP(size),
>> + iotlbentry->attrs);
>> if (r != MEMTX_OK) {
>> hwaddr physaddr = mr_offset +
>> section->offset_within_address_space -
>> --
>> 1.8.3.1
>>
>
> Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Hmm now reading patch #11 I think you should also convert
cpu_transaction_failed() in this patch, not in #11, and this will make
#11 easier to review.
- [Qemu-riscv] [Qemu-devel] [PATCH v4 01/15] tcg: TCGMemOp is now accelerator independent MemOp, (continued)
- [Qemu-riscv] [Qemu-devel] [PATCH v4 01/15] tcg: TCGMemOp is now accelerator independent MemOp, tony.nguyen, 2019/07/25
- [Qemu-riscv] [Qemu-devel] [PATCH v4 04/15] hw/s390x: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-riscv] [Qemu-devel] [PATCH v4 05/15] hw/intc/armv7m_nic: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-riscv] [Qemu-devel] [PATCH v4 06/15] hw/virtio: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-riscv] [Qemu-devel] [PATCH v4 07/15] hw/vfio: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-riscv] [Qemu-devel] [PATCH v4 08/15] exec: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-riscv] [Qemu-devel] [PATCH v4 09/15] cputlb: Access MemoryRegion with MemOp, tony.nguyen, 2019/07/25
- [Qemu-riscv] [Qemu-devel] [PATCH v4 10/15] memory: Access MemoryRegion with MemOp semantics, tony.nguyen, 2019/07/25
- [Qemu-riscv] [Qemu-devel] [PATCH v4 11/15] memory: Single byte swap along the I/O path, tony.nguyen, 2019/07/25
- [Qemu-riscv] [Qemu-devel] [PATCH v4 12/15] cpu: TLB_FLAGS_MASK bit to force memory slow path, tony.nguyen, 2019/07/25
- [Qemu-riscv] [Qemu-devel] [PATCH v4 13/15] cputlb: Byte swap memory transaction attribute, tony.nguyen, 2019/07/25
- [Qemu-riscv] [Qemu-devel] [PATCH v4 14/15] target/sparc: Add TLB entry with attributes, tony.nguyen, 2019/07/25
- [Qemu-riscv] [Qemu-devel] [PATCH v4 15/15] target/sparc: sun4u Invert Endian TTE bit, tony.nguyen, 2019/07/25