[Qemu-riscv] [PATCH-4.2 v1 0/6] RISC-V: Hypervisor prep work part 2

[Alistair Francis]

The first four patches are ones that I have pulled out of my original
Hypervisor series at an attempt to reduce the number of patches in the
series.

These four patches all make sense without the Hypervisor series so can
be merged seperatley and will reduce the review burden of the next
version of the patches.

The fifth patch is a prep patch for the new v0.4 Hypervisor spec.

The final patch is unreleated to Hypervisor that I'm just slipping in
here because it seems easier then sending it by itself.

Alistair Francis (5):
  target/riscv: Don't set write permissions on dirty PTEs
  target/riscv: Remove strict perm checking for CSR R/W
  riscv: plic: Remove unused interrupt functions
  target/riscv: Create function to test if FP is enabled
  target/riscv: Update the Hypervisor CSRs to v0.4

Atish Patra (1):
  target/riscv: Fix Floating Point register names

 hw/riscv/sifive_plic.c         | 12 ------------
 include/hw/riscv/sifive_plic.h |  3 ---
 target/riscv/cpu.c             |  8 ++++----
 target/riscv/cpu.h             |  6 +++++-
 target/riscv/cpu_bits.h        | 35 +++++++++++++++++-----------------
 target/riscv/cpu_helper.c      | 16 ++++++++++++----
 target/riscv/csr.c             | 22 ++++++++++-----------
 7 files changed, 50 insertions(+), 52 deletions(-)

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2.22.0