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[Qemu-riscv] [PATCH v2 17/28] riscv: sifive_u: Change UART node name in
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From: |
Bin Meng |
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Subject: |
[Qemu-riscv] [PATCH v2 17/28] riscv: sifive_u: Change UART node name in device tree |
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Date: |
Wed, 7 Aug 2019 00:45:13 -0700 |
OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating
chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will
use this information to locate the serial node and probe its driver.
However currently we generate the UART node name as "/soc/uart@...",
causing U-Boot fail to find the serial node in DT.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
Changes in v2: None
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index cab329a..bddf892 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -274,7 +274,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
g_free(nodename);
- nodename = g_strdup_printf("/soc/uart@%lx",
+ nodename = g_strdup_printf("/soc/serial@%lx",
(long)memmap[SIFIVE_U_UART0].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
--
2.7.4
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, (continued)
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Alistair Francis, 2019/08/09
[Qemu-riscv] [PATCH v2 10/28] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/07
[Qemu-riscv] [PATCH v2 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/07
[Qemu-riscv] [PATCH v2 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/07
[Qemu-riscv] [PATCH v2 05/28] riscv: hart: Support heterogeneous harts population, Bin Meng, 2019/08/07
[Qemu-riscv] [PATCH v2 13/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/07
[Qemu-riscv] [PATCH v2 22/28] riscv: sifive_u: Generate an aliases node in the device tree, Bin Meng, 2019/08/07
[Qemu-riscv] [PATCH v2 17/28] riscv: sifive_u: Change UART node name in device tree,
Bin Meng <=
[Qemu-riscv] [PATCH v2 16/28] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/07
[Qemu-riscv] [PATCH v2 14/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/07
[Qemu-riscv] [PATCH v2 25/28] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/08/07
[Qemu-riscv] [PATCH v2 18/28] riscv: hw: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/07
[Qemu-riscv] [PATCH v2 24/28] riscv: sifive_u: Support loading initramfs, Bin Meng, 2019/08/07
[Qemu-riscv] [PATCH v2 23/28] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/07
[Qemu-riscv] [PATCH v2 27/28] riscv: virt: Change create_fdt() to return void, Bin Meng, 2019/08/07