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[Qemu-riscv] [PATCH v3 24/28] riscv: sifive_u: Support loading initramfs
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From: |
Bin Meng |
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Subject: |
[Qemu-riscv] [PATCH v3 24/28] riscv: sifive_u: Support loading initramfs |
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Date: |
Sun, 11 Aug 2019 01:06:57 -0700 |
The loading of initramfs is currently not supported on 'sifive_u'.
Add the support to make '-initrd' command line parameter useful.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
---
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e8bef44..b0026aa 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -328,7 +328,18 @@ static void riscv_sifive_u_init(MachineState *machine)
memmap[SIFIVE_U_DRAM].base);
if (machine->kernel_filename) {
- riscv_load_kernel(machine->kernel_filename);
+ uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
+
+ if (machine->initrd_filename) {
+ hwaddr start;
+ hwaddr end = riscv_load_initrd(machine->initrd_filename,
+ machine->ram_size, kernel_entry,
+ &start);
+ qemu_fdt_setprop_cell(s->fdt, "/chosen",
+ "linux,initrd-start", start);
+ qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
+ end);
+ }
}
/* reset vector */
--
2.7.4
- [Qemu-riscv] [PATCH v3 16/28] riscv: sifive_u: Add PRCI block to the SoC, (continued)
- [Qemu-riscv] [PATCH v3 16/28] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 17/28] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 14/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 18/28] riscv: hw: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 22/28] riscv: sifive_u: Generate an aliases node in the device tree, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 21/28] riscv: sifive_u: Update UART and ethernet node clock properties, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 24/28] riscv: sifive_u: Support loading initramfs,
Bin Meng <=
- [Qemu-riscv] [PATCH v3 23/28] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 25/28] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 27/28] riscv: virt: Change create_fdt() to return void, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 28/28] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/08/11
- Re: [Qemu-riscv] [PATCH v3 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Bin Meng, 2019/08/11