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Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 05/28] riscv: hart: Support hete
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 05/28] riscv: hart: Support heterogeneous harts population |
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Date: |
Sun, 11 Aug 2019 08:56:56 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 |
On 8/11/19 1:06 AM, Bin Meng wrote:
> + /* heterogeneous harts */
> + while (tmp_type) {
> + if (n >= s->num_harts) {
> + break;
> + }
> + riscv_hart_realize(s, n++, tmp_type, errp);
> + last_type = tmp_type;
> + tmp_type = strtok(NULL, ",");
> + }
You need to create clusters for each cpu type.
In particular, E51 does not have the fpu that U54 does, and so we need to
generate different code for each cluster.
Because each cluster generates different TBs, you'll minimize code generation
if you do more than just create one per cpu, e.g. pop these cpu type names into
a GHashTable as you create each cluster.
The only other example of clusters in tree is hw/arm/armsse.c. Note that board
has one cpu per cluster, as each cpu may be configured differently via other
property settings.
r~
- [Qemu-riscv] [PATCH v3 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 01/28] riscv: hw: Remove superfluous "linux, phandle" property, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 04/28] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 05/28] riscv: hart: Support heterogeneous harts population, Bin Meng, 2019/08/11
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 05/28] riscv: hart: Support heterogeneous harts population,
Richard Henderson <=
- [Qemu-riscv] [PATCH v3 08/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 07/28] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 10/28] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 09/28] riscv: sifive_u: Update UART base addresses and IRQs, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/11
- [Qemu-riscv] [PATCH v3 13/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/11