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Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 17/30] riscv: sifive_u: Set the
From: |
Alistair Francis |
Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 17/30] riscv: sifive_u: Set the minimum number of cpus to 2 |
Date: |
Fri, 23 Aug 2019 11:34:14 -0700 |
On Thu, Aug 22, 2019 at 10:16 PM Bin Meng <address@hidden> wrote:
>
> It is not useful if we only have one management CPU.
>
> Signed-off-by: Bin Meng <address@hidden>
> Reviewed-by: Alistair Francis <address@hidden>
Ah, I jumped the gun with patch 16. This should be before patch 16,
otherwise patch 16 is fine.
Alistair
>
> ---
>
> Changes in v5: None
> Changes in v4: None
> Changes in v3:
> - use management cpu count + 1 for the min_cpus
>
> Changes in v2:
> - update the file header to indicate at least 2 harts are created
>
> hw/riscv/sifive_u.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 0e5bbe7..a36cd77 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -10,8 +10,8 @@
> * 1) CLINT (Core Level Interruptor)
> * 2) PLIC (Platform Level Interrupt Controller)
> *
> - * This board currently generates devicetree dynamically that indicates at
> most
> - * five harts.
> + * This board currently generates devicetree dynamically that indicates at
> least
> + * two harts and up to five harts.
> *
> * This program is free software; you can redistribute it and/or modify it
> * under the terms and conditions of the GNU General Public License,
> @@ -485,6 +485,7 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
> mc->desc = "RISC-V Board compatible with SiFive U SDK";
> mc->init = riscv_sifive_u_init;
> mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT +
> SIFIVE_U_COMPUTE_CPU_COUNT;
> + mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
> }
>
> DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
> --
> 2.7.4
>
>
- [Qemu-riscv] [PATCH v5 07/30] riscv: roms: Remove executable attribute of opensbi images, (continued)
- [Qemu-riscv] [PATCH v5 07/30] riscv: roms: Remove executable attribute of opensbi images, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 08/30] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 11/30] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 14/30] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 17/30] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/23
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v5 17/30] riscv: sifive_u: Set the minimum number of cpus to 2,
Alistair Francis <=
- [Qemu-riscv] [PATCH v5 18/30] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 16/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 23/30] riscv: sifive_u: Update UART base addresses and IRQs, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 19/30] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 21/30] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/23
- [Qemu-riscv] [PATCH v5 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Bin Meng, 2019/08/23